UWOrbital / OBC-firmwareLinks
All code developed by the UW Orbital firmware team
☆20Updated this week
Alternatives and similar repositories for OBC-firmware
Users that are interested in OBC-firmware are comparing it to the libraries listed below
Sorting:
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆30Updated last month
- SystemVerilog Tutorial☆166Updated 3 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆23Updated 7 months ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆139Updated 3 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆265Updated 3 months ago
- opensource EDA tool flor VLSI design☆33Updated last year
- 100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…☆27Updated 2 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆81Updated 2 months ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆23Updated last month
- ☆94Updated 3 months ago
- Basic RISC-V Test SoC☆140Updated 6 years ago
- Pipelined RISC-V RV32I Core in Verilog☆39Updated 2 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆143Updated 4 years ago
- A Reconfigurable RISC-V Core for Approximate Computing☆125Updated 3 months ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆13Updated 9 months ago
- For aspiring hardware engineers out there.☆72Updated 5 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆112Updated last week
- ☆15Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆135Updated 2 weeks ago
- ☆36Updated last month
- Single Cycle 32 bit MIPS☆20Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆156Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- ECE 350: Real-Time Operating Systems☆25Updated 4 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆17Updated 4 years ago
- lowRISC Style Guides☆450Updated 2 months ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆402Updated last week
- Pipeline FFT Implementation in Verilog HDL☆131Updated 6 years ago