Alternatives and similar repositories for sse2rvv:

Users that are interested in sse2rvv are comparing it to the libraries listed below

• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆42Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• UCTECHIP / rocket_chip_vpu
  ☆11Updated 4 years ago
• i-evi / sse2msa
  A C/C++ header file that converts Intel SSE intrinsics to MIPS/MIPS64 MSA intrinsics.
  ☆10Updated 3 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 2 years ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆12Updated last year
• pulp-platform / hero-sdk
  ⛔ DEPRECATED ⛔ HERO Software Development Kit
  ☆20Updated 3 years ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆12Updated last month
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 6 years ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 5 years ago
• CMU-SAFARI / BEER
  BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…
  ☆19Updated 4 years ago
• ucb-bar / riscv-blas
  Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V
  ☆19Updated 5 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆47Updated last month
• vortexgpgpu / pocl
  a clone of POCL that includes RISC-V newlib devices support and Vortex
  ☆41Updated last month
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆35Updated 2 weeks ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated 2 months ago
• openhwgroup / corev-llvm-project
  ☆13Updated 9 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• pulp-platform / chimera
  ☆16Updated 2 weeks ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆32Updated 10 years ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 8 years ago
• vortexgpgpu / NVPTX-SPIRV-Translator
  The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.
  ☆38Updated 3 years ago
• oprecomp / flexfloat
  C library for the emulation of reduced-precision floating point types
  ☆49Updated 2 years ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated 2 months ago
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆33Updated 8 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆111Updated this week