Alternatives and similar repositories for softcoreA

Users that are interested in softcoreA are comparing it to the libraries listed below

• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆64Updated this week
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆64Updated 3 weeks ago
• nfinit / ansibench
  A selection of ANSI C benchmarks and programs useful as benchmarks
  ☆99Updated 3 weeks ago
• CTSRD-CHERI / cheribuild
  Easily build and run CHERI related projects
  ☆86Updated this week
• larkmjc / riscv-meta
  RISC-V Instruction Set Metadata
  ☆42Updated 7 years ago
• CTSRD-CHERI / cheribsd
  FreeBSD adapted for CHERI-RISC-V and Arm Morello.
  ☆204Updated this week
• CTSRD-CHERI / cheri-c-programming
  CHERI C/C++ Programming Guide
  ☆40Updated this week
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆63Updated 4 years ago
• larkmjc / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆193Updated last month
• sifiveinc / wake
  The SiFive wake build tool
  ☆92Updated this week
• CTSRD-CHERI / cherios
  CheriOS -- a minimal microkernel that demonstrates "clean-slate" CHERI memory protection and object capabilities
  ☆42Updated 3 years ago
• seL4 / microkit
  Microkit - A simple operating system framework for the seL4 microkernel
  ☆169Updated 2 weeks ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆34Updated last week
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 6 months ago
• openhwgroup / corev-gcc
  ☆26Updated last year
• cattius / opcodetester
  Tool for automated testing and analysis of Intel x86-64 undocumented instructions in user mode and in the kernel
  ☆46Updated 6 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆47Updated 5 months ago
• riscvarchive / riscv-code-size-reduction
  ☆148Updated last year
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆48Updated 3 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆52Updated 8 months ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆61Updated 5 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆92Updated 3 weeks ago
• seL4 / seL4_libs
  No-assurance libraries for rapid-prototyping of seL4 apps.
  ☆57Updated last week
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated last year
• CHERIoT-Platform / cheriot-sail
  Sail code model of the CHERIoT ISA
  ☆48Updated last month
• openpower-cores / a2o
  ☆144Updated 3 years ago
• jamesbowman / j1
  The J1 CPU
  ☆173Updated 5 years ago