Alternatives and similar repositories for IPECC

Users that are interested in IPECC are comparing it to the libraries listed below

• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆37Updated 4 years ago
• ascon / ascon-hardware
  NIST LWC Hardware Reference Implementation of Ascon v1.2
  ☆31Updated 2 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 3 years ago
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆34Updated 3 months ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated 2 months ago
• Ko- / riscvcrypto
  Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture
  ☆31Updated 5 years ago
• ANSSI-FR / SecAESSTM32
  Bibliothèque C et assembleur permettant le chiffrement/déchiffrement AES-128 de messages pour des composants grand public (famille STM32F…
  ☆69Updated 3 years ago
• isec-tugraz / ascon_hardware
  Hardware implementations of the authenticated encryption design ASCON
  ☆19Updated 8 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆12Updated 6 years ago
• isec-tugraz / memsec
  Framework for building transparent memory encryption and authentication solutions
  ☆27Updated 7 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 8 years ago
• ascon / ascon-hardware-sca
  NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks
  ☆19Updated 2 years ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 5 years ago
• simple-crypto / SCALib
  Side-Channel Analysis Library
  ☆105Updated 4 months ago
• secworks / blake2s
  Verilog implementation of the 32-bit version of the Blake2 hash function
  ☆21Updated last month
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆54Updated 5 years ago
• hyperpicc / ecc
  Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)
  ☆22Updated 8 years ago
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 5 years ago
• ANSSI-FR / secAES-ATmega8515
  Secure AES128 Encryption Implementation for ATmega8515
  ☆35Updated 4 years ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆78Updated 5 years ago
• slh-dsa / sloth
  SLotH -- An SLH-DSA/SPHINCS+ Hash-Based Signature Accelerator
  ☆39Updated 10 months ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated last year
• kudelskisecurity / Verilaptor
  ☆21Updated 4 years ago
• raymondrc / riscv-isa-extension-for-SM4
  RISC-V instruction set extensions for SM4 block cipher
  ☆21Updated 5 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆24Updated 8 years ago
• lennartbublies / ecdsa
  ECDSA VHDL Implementation
  ☆12Updated 7 years ago
• ileanabuhan / Tutorial-on-entropies
  An interactive notebook for understanding the relation between mutual information, perceived and hypothetical information
  ☆11Updated 5 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆42Updated last month
• ljhsiun2 / EllipticCurves_SystemVerilog
  Elgamal's over Elliptic Curves
  ☆19Updated 7 years ago