https://github.com/dendibakh/perf-book gitbook在线电子书，翻译成中文原始markdown文档
☆117Dec 30, 2024Updated last year
Alternatives and similar repositories for perf-book-cn
Users that are interested in perf-book-cn are comparing it to the libraries listed below
Sorting:
- ☆11Dec 23, 2025Updated 2 months ago
- 【2024年新版】国科大 陈云霁 智能计算系统AICS实验代码☆13May 31, 2024Updated last year
- gem5 FS模式实验手册☆44Mar 8, 2023Updated 3 years ago
- ☆17May 9, 2022Updated 3 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Updated this week
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- 《Performance Analysis and Tuning on Modern CPUS - 2ed》的非专业个人翻译☆60Jan 8, 2025Updated last year
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。☆22Nov 24, 2024Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- Microarchitecture diagrams of several CPUs☆47Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 3 months ago
- ☆13Jan 16, 2026Updated last month
- 经典的嵌入式OS - ucos-II 2.52版本全注释，仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- A Study of the SiFive Inclusive L2 Cache☆69Dec 27, 2023Updated 2 years ago
- A Flexible Cache Architectural Simulator☆17Sep 16, 2025Updated 5 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆16Updated this week
- ☆13May 8, 2025Updated 10 months ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Updated this week
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago
- ☆129Updated this week
- ☆30Jan 23, 2025Updated last year
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- 关于移植模型至gemmini的文档☆33May 4, 2022Updated 3 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Feb 20, 2024Updated 2 years ago
- Simulator or Non-Uniform Cache Architectures☆10Aug 27, 2018Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆200Oct 14, 2024Updated last year
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆34Jun 16, 2023Updated 2 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Sep 29, 2024Updated last year
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Tiny raytracer with stochastic sampling and thin lens model☆18Aug 8, 2021Updated 4 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 3 months ago
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- RISC-V is where innovation happens!☆19Dec 25, 2023Updated 2 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Jul 25, 2024Updated last year
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 3 months ago
- Readings in Computer Architectures☆17Dec 21, 2025Updated 2 months ago