jdmccalpin / Intel_Address_HashLinks
Use hardware performance counters to find mapping of addresses to L3 slices in Intel processors
☆17Updated 2 years ago
Alternatives and similar repositories for Intel_Address_Hash
Users that are interested in Intel_Address_Hash are comparing it to the libraries listed below
Sorting:
- BTB-X HPCA23 code☆11Updated 2 years ago
 - Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆29Updated 4 months ago
 - ☆18Updated 3 years ago
 - Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆38Updated 3 years ago
 - Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor☆20Updated last year
 - HW interface for memory caches☆28Updated 5 years ago
 - The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆22Updated last year
 - ☆18Updated last year
 - This upload contains the artifacts for the paper "SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon", to appear…☆22Updated 9 months ago
 - Tool for inferring cache replacement policies with automata learning. Uses LearnLib and Sketch.☆16Updated 5 years ago
 - Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆30Updated 2 years ago
 - Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 4 years ago
 - Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…☆26Updated last year
 - Microarchitectural weird machine implementation using exceptions, TSX, branch predictors, and branch target buffers.☆16Updated 2 years ago
 - Implementation for the DIMVA'22 paper "Branch Different - Spectre Attacks on Apple Silicon"☆36Updated 3 years ago
 - GPUReplay, ASPLOS 2022☆41Updated 3 years ago
 - ☆40Updated 3 months ago
 - Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆25Updated last year
 - ☆17Updated 4 months ago
 - ☆15Updated 7 months ago
 - Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
 - Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]☆63Updated last year
 - Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆29Updated 7 months ago
 - Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆22Updated this week
 - Repeated access to L2-containable loops to look for snoop filter conflicts on Intel Skylake Xeon processors.☆29Updated 7 years ago
 - Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆20Updated 3 years ago
 - Proof-of-concept implementation for the paper "Indirect Meltdown: Building Novel Side-Channel Attacks from Transient Execution Attacks" (…☆22Updated 2 years ago
 - The open-source component of Prime+Scope, published at CCS 2021☆35Updated 2 years ago
 - Proof-of-concept implementation for the paper "SegScope: Probing Fine-grained Interrupts via Architectural Footprints" (HPCA'24)☆19Updated 10 months ago
 - NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]☆18Updated 2 years ago