jdmccalpin / Intel_Address_HashLinks
Use hardware performance counters to find mapping of addresses to L3 slices in Intel processors
☆17Updated 2 years ago
Alternatives and similar repositories for Intel_Address_Hash
Users that are interested in Intel_Address_Hash are comparing it to the libraries listed below
Sorting:
- BTB-X HPCA23 code☆11Updated 2 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆26Updated 3 months ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆37Updated 3 years ago
- ☆18Updated 3 years ago
- HW interface for memory caches☆28Updated 5 years ago
- Microarchitectural weird machine implementation using exceptions, TSX, branch predictors, and branch target buffers.☆15Updated 2 years ago
- ☆40Updated 2 months ago
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆22Updated last year
- Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor☆20Updated last year
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- Repeated access to L2-containable loops to look for snoop filter conflicts on Intel Skylake Xeon processors.☆29Updated 7 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆22Updated 3 years ago
- ☆15Updated 2 years ago
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆11Updated 8 years ago
- Proof-of-concept implementation for the paper "SegScope: Probing Fine-grained Interrupts via Architectural Footprints" (HPCA'24)☆19Updated 9 months ago
- Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆30Updated 2 years ago
- This upload contains the artifacts for the paper "SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon", to appear…☆20Updated 8 months ago
- Hypervisor written in Rust for the RISC-V 1.0 hypervisor extension☆16Updated 11 months ago
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆20Updated 3 years ago
- Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]☆63Updated last year
- MIRAGE (USENIX Security 2021)☆13Updated last year
- Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆24Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆27Updated 3 months ago
- A library for PCIe Transaction Layer☆60Updated 3 years ago
- ☆17Updated 3 months ago
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- some tlb experimentation code: calculate L1, L2 miss penalties and show cross-HT interference.☆14Updated 6 years ago
- ☆16Updated 10 months ago
- Tool for inferring cache replacement policies with automata learning. Uses LearnLib and Sketch.☆16Updated 5 years ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆22Updated 2 weeks ago