Alternatives and similar repositories for learning-riscv

Users that are interested in learning-riscv are comparing it to the libraries listed below

• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆233Updated 4 years ago
• sunshaoce / rvcc-course
  ☆95Updated last year
• sunshaoce / rvcc
  本课程基于Rui的chibicc，@sunshaoce和@ksco将其由原来的X86架构改写为RISC-V 64架构，同时加入了大量的中文注释，并且配有316节对应于每一个commit的课程，帮助读者可以层层推进、逐步深入的学习编译器的构造。
  ☆359Updated 2 years ago
• runninglinuxkernel / riscv_programming_practice
  ☆224Updated 2 years ago
• NJU-ProjectN / fceux-am
  ☆102Updated last month
• nkgongxl / ucoreonrv
  ☆51Updated 5 years ago
• NJU-ProjectN / am-kernels
  AbstractMachine kernels
  ☆68Updated last week
• kaitoukito / A-Primer-on-Memory-Consistency-and-Cache-Coherence
  A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划
  ☆321Updated last year
• hellollvm / nanpanjiang-project
  由HelloLLVM社区主席邱吉博士发起，联合HelloGCC等技术社区，推出了「南盘江计划」，致力于帮助更多的女性工程师在编译等基础软件领域实现个人职业目标。
  ☆39Updated 5 months ago
• shzhxh / xv6-riscv-book-CN
  xv6-riscv-book中译版
  ☆83Updated last year
• Hanseltu / kaleidoscope-tutorial
  My First Language Frontend with LLVM Tutorial in Chinese
  ☆80Updated 2 years ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆93Updated 7 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆180Updated 4 years ago
• P2Tree / LLVM_for_cpu0
  This is a tutorial to learn LLVM, I realize a backend to compiler machine code for cpu0 which is a simple RISC cpu.
  ☆266Updated 3 years ago
• weedge / perf-book-cn
  https://github.com/dendibakh/perf-book gitbook在线电子书，翻译成中文原始markdown文档
  ☆113Updated 11 months ago
• hunterzju / llvm-tutorial
  llvm-tutorial文档，翻译以及代码仓库
  ☆169Updated 2 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆200Updated last year
• plctlab / PLCT-Weekly
  软件所PLCT实验室在开源领域的不定期简报
  ☆645Updated 2 weeks ago
• weiox / remu
  使用 C++23 从零实现的 RISC-V 模拟器
  ☆33Updated 10 months ago
• TuringKi / Gitbook-Computer-Architecture-A-Quantitative-Approach-6th-Chinese
  【持续更新中】计算机体系结构：量化研究方法（第六版）汉化
  ☆42Updated 3 years ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆45Updated 2 years ago
• OpenXiangShan / NEMU
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆303Updated this week
• iiicp / subc-llvm
  实现一个子集c编译器，后端基于llvm20
  ☆11Updated 9 months ago
• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆161Updated 3 months ago
• HUST-OS / xv6-k210
  Port XV6 to K210 board!
  ☆144Updated 4 years ago
• ksco / rvemu
  A simple and fast RISC-V JIT emulator.
  ☆154Updated last year
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆296Updated 3 months ago
• xiaoweiChen / LLVM-Techniques-Tips-and-Best-Practies
  《LLVM Techniques, Tips, and Best Practices》的非专业个人翻译
  ☆135Updated 3 years ago
• xiaoyu1998 / llvm-cpu0
  LLVM Backend tutorial Cpu0
  ☆25Updated 2 years ago
• xiaoweiChen / Learn-LLVM-17
  《Learn LLVM 17》的非专业个人翻译
  ☆155Updated last year