Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGAView on GitHub
A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.
☆14Oct 13, 2025Updated last year

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