5 Stage Pipelined RISC-V SoC with Hardware Enforced CFI, Dual Port Synchronous Memory Controller and Bidirectional UART implemented in VHDL from Scratch
☆16Jun 27, 2026Updated last month
Alternatives and similar repositories for eSC-V
Users that are interested in eSC-V are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Portable four-parameter vital signs monitor (ECG, SpO2, temperature, respiration) built on ESP32. Biomedical engineering bachelor's proje…☆16Jul 9, 2026Updated last month
- A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication☆42Jul 13, 2026Updated 3 weeks ago
- Kiln — WebAssembly runtime for safety-critical systems. Full Component Model and WASI 0.2 support. Part of the PulseEngine toolchain.☆15Aug 3, 2026Updated last week
- ☆12Jun 8, 2018Updated 8 years ago
- Projects with Software Defined Radio (SDR) for Computer Networks Class☆16Dec 1, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- An Open-Source Analog Mixed-Signal Chip Design Template & Tutorial for the ihp-sg13g2 Open-PDK☆41Aug 3, 2026Updated last week
- UVM☆14Mar 16, 2020Updated 6 years ago
- impl Rust for Raspberry Pi Pico - Embedded Programming with Raspberry Pi Pico (RP2040) and Rust☆16Aug 2, 2026Updated last week
- ☆32Jun 18, 2026Updated last month
- ☆17Oct 13, 2024Updated last year
- Design of an image generator to represent a street scene. Can be used as a stand-alone design for image generator or as a test pattern ge…☆11Nov 18, 2019Updated 6 years ago
- Collection of AI, Data Structures, Data Science, DBMS, and OOP practicals implemented in Python, aligned with the SPPU 2024 curriculum. I…☆23Updated this week
- Design and Simulation of 1K * 32 bit SRAM memory design.☆23Dec 15, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 5 months ago
- Interactive 3D Layout Viewer for GDSII☆19Jun 14, 2024Updated 2 years ago
- ☆15Aug 3, 2021Updated 5 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆65Mar 21, 2024Updated 2 years ago
- ☆22Jun 14, 2026Updated last month
- Open-source IoT coding agent for ESP32/ESP-IDF and Nordic nRF (NCS/Zephyr): build, flash, and debug firmware on real hardware, plus one-c…☆25Jul 22, 2026Updated 2 weeks ago
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆15Aug 2, 2026Updated last week
- Python Library to automate messaging on whatsapp to unlimited people without having to actually save the number of the particular person☆16Oct 14, 2025Updated 9 months ago
- Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with…☆19Jul 21, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Repository for the Introduction to FPGA Programming Using Xilinx Vivado and VHDL PhD course at University of Torino, Physics Department.☆25Jul 4, 2025Updated last year
- Testfield: T593☆15Apr 27, 2026Updated 3 months ago
- Team memory sharing for claude-mem — sync AI memories across developers, with Claude Code plugin, github action and knowledge distillatio…☆20Jun 20, 2026Updated last month
- use Zybo z7-20☆17May 21, 2025Updated last year
- Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC☆27Sep 1, 2021Updated 4 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- UEFI firmware for RK3576 devices☆16Updated this week
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- Facilitating Interoperability in Open RAN☆18Jul 13, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.☆27Feb 28, 2024Updated 2 years ago
- Python Telegram bot API framework☆18Aug 29, 2020Updated 5 years ago
- TelecomTS: A Multi-Modal Telecom Dataset☆15May 27, 2026Updated 2 months ago
- The py3gppchannels library is a Python package that implements the 3GPP standardized radio channel models (3GPP TR 38.901). It provides a…☆18Sep 17, 2023Updated 2 years ago
- Official Webpage of Swaroop2sky.☆12Mar 2, 2025Updated last year
- Analog HDL Design Full-stack Agents☆18Jun 8, 2026Updated 2 months ago
- High Performance Erlang Kafka Producer☆17Nov 20, 2023Updated 2 years ago