☆14Dec 6, 2022Updated 3 years ago
Alternatives and similar repositories for kb_radar_course
Users that are interested in kb_radar_course are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OSVVM Ethernet Library☆10Oct 9, 2026Updated last month
- Implementation of the Xilinx FFT IP using a UART packetised data stream☆13Jul 24, 2022Updated 4 years ago
- FPGA BASED RADAR ACQUISITION AND PREPROCESSING UNIT☆10Jul 3, 2020Updated 6 years ago
- ESnet general-purpose FPGA design library.☆14Nov 3, 2026Updated last week
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆32Dec 10, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A collection of Opal Kelly provided design resources☆19Nov 2, 2026Updated last week
- 6GHz frequency-modulated continuous-wave radar with real-time range detection☆67Sep 20, 2020Updated 6 years ago
- Logic Input Triggered High-resolution Pulser☆13Mar 24, 2020Updated 6 years ago
- ☆11Oct 10, 2026Updated last month
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- ☆20Updated this week
- A Constant False Alarm Rate Processor Generator☆11Apr 13, 2023Updated 3 years ago
- Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.☆35Jul 30, 2020Updated 6 years ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Official implementation of paper "MCST: An adaptive tracking algorithm for high-speed and highly maneuverable targets based on bidirecti…☆13Oct 31, 2025Updated last year
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Vivado project for Xilinx Artix FPGA, used in logic analyzer☆15Jul 16, 2021Updated 5 years ago
- High-througput logic analyzer for FPGA☆17Oct 8, 2020Updated 6 years ago
- Half-precision floating point for NumPy☆13Nov 10, 2010Updated 16 years ago
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆18Jul 11, 2015Updated 11 years ago
- JESD204b modules in VHDL☆31Apr 18, 2019Updated 7 years ago
- Software Defined Range Radar using PlutoSDR☆14May 12, 2023Updated 3 years ago
- Collection of assorted small cores☆13Oct 6, 2020Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- A curated list of FMCW-LiDAR papers and resources.☆39May 19, 2026Updated 5 months ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 9 years ago
- Collection of hardware description languages writings and code snippets☆31Jan 29, 2015Updated 11 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)☆11Sep 25, 2026Updated last month
- This is the repository of through-the-wall radar human activity recognition using multi-sampling convolutional neural networks (MSCNN). A…☆10Aug 5, 2025Updated last year
- Dual-Mode PSK Transceiver on SDR With FPGA☆60Oct 9, 2024Updated 2 years ago
- Парсинг сайтов недвижимости☆25Dec 8, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 7 years ago
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆16Jan 3, 2022Updated 4 years ago
- An abstract model of EDA tool projects.☆14Updated this week
- ☆11Apr 20, 2022Updated 4 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- Codes for femtosecond laser interaction research☆13Aug 10, 2026Updated 3 months ago
- ZF2 module contain using Ajax in Zend\Form☆13Mar 5, 2013Updated 13 years ago
Are these results useful?