Alternatives and similar repositories for rdimm-ddr4-tester:

Users that are interested in rdimm-ddr4-tester are comparing it to the libraries listed below

• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last week
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆27Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 3 weeks ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆25Updated 5 years ago
• antmicro / lpddr4-testbed
  Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.
  ☆13Updated 9 months ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆33Updated last year
• grayresearch / s4ga
  a small simple slow serial FPGA core
  ☆16Updated 3 years ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆49Updated 4 years ago
• xyzxinyizhang / FPGA-SFP-communication-with-Aurora
  ☆17Updated 6 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆18Updated 10 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆35Updated 9 months ago
• sergachev / litex-template
  Template project for LiteX-based SoCs
  ☆19Updated 6 months ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆35Updated 2 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 3 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆40Updated last week
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆42Updated 2 years ago
• regymm / SqueakyBoard
  My self-designed ZYNQ-7010 4-layer developement board.
  ☆29Updated 3 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆29Updated 4 years ago
• litex-hub / wishbone-utils
  Utilities for working with a Wishbone bus in an embedded device
  ☆41Updated 11 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆25Updated 3 months ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆24Updated last year