Alternatives and similar repositories for CedarLogic

Users that are interested in CedarLogic are comparing it to the libraries listed below

• kittybupu / openVCB
  An open source implementation of the Virtual Circuit Board loader, assembler, and simulation engine.
  ☆88Updated 2 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆14Updated 3 years ago
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆72Updated last month
• mikeakohn / riscv_fpga
  Implementation of a RISC-V CPU in Verilog.
  ☆17Updated 7 months ago
• leijurv / Logisim-RISC-V
  ☆39Updated 7 years ago
• TinyTapeout / tt02-submission-template
  Submission template for TT02
  ☆25Updated 2 years ago
• pineapple-one / logisim-simulation
  Simulation in Logisim-Evolution HC
  ☆34Updated 4 years ago
• TheCodingTurtle / tortlecard
  All the files for my 16-bit GPU called the turtle card 200X3D.
  ☆17Updated 5 months ago
• cnlohr / embeddedDOOM
  "emdoom" - a port of DOOM targeted for memory-strapped systems.
  ☆118Updated 2 years ago
• nickmqb / fpga_craft
  A voxel game/Minecraft clone for the iCE40 UP5K FPGA
  ☆209Updated 4 years ago
• cnlohr / badderapple
  Bad Apple in 65kB or bust.
  ☆32Updated last week
• ccattuto / riscv-python
  RISC-V Emulator in pure Python (RV32I, machine mode, Newlib support, memory-mapped IO)
  ☆20Updated 2 months ago
• TinyTapeout / tinytapeout-03
  ☆16Updated last year
• lushaylabs / lushay-code
  yosys, nextpnr, apicula and openFPGALoader in vscode using OSS-CAD-Suite
  ☆34Updated last year
• mkvenkit / humble_ice
  A low cost FPGA development board based on Lattice iCE40UP5k and Raspberry Pi RP2040.
  ☆45Updated 3 years ago
• Johnlon / spam-1
  Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my r…
  ☆68Updated 2 years ago
• Kenny2github / V2MC
  Synthesize Verilog to Minecraft redstone
  ☆18Updated 11 months ago
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆17Updated 4 years ago
• jrmoserbaltimore / risc-v-cpu-asynchronous
  A RISC-V CPU implementation
  ☆14Updated 5 years ago
• YoWASP / vscode
  YoWASP toolchain for Visual Studio Code
  ☆20Updated 3 months ago
• mortie / rv32i-logisim-cpu
  Implementation of RV32I in Logisim-evolution.
  ☆24Updated 2 years ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 3 years ago
• bitluni / luniASM
  ☆63Updated last year
• riktw / HUB75E_ICE40
  SpinalHDL code to drive a 64*64 pixel HUB75E module with an ICE40
  ☆32Updated 5 years ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆101Updated 2 years ago
• ICE-V-Wireless / ICE-V-Wireless
  Combined ESP32C3 and iCE40 FPGA board
  ☆71Updated last week
• amstan / qoi-fpga
  Quite OK Image FPGA Encoder and Decoder
  ☆23Updated 2 years ago
• calint / tang-nano-9k--riscv--cache-psram
  RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
  ☆40Updated last month
• sifferman / fpga_screensaver
  This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board…
  ☆13Updated 2 years ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year