youtubezou / thinking-in-csLinks
computer science
☆33Updated 6 years ago
Alternatives and similar repositories for thinking-in-cs
Users that are interested in thinking-in-cs are comparing it to the libraries listed below
Sorting:
- ☆29Updated 4 years ago
- Linux Kernel Debugging, published by Packt☆184Updated last year
- Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.☆36Updated last year
- KVM RISC-V HowTOs☆47Updated 3 years ago
- ☆72Updated 2 years ago
- A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw☆122Updated 3 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Updated 9 months ago
- RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-…☆629Updated 2 years ago
- Linux 0.12 with GCC 11.2.0☆30Updated 2 years ago
- Tiny simple things inside the kernel☆27Updated 7 months ago
- Operating Systems Design and Implementation Notes☆47Updated last year
- [WIP] Xv6, a simple Unix-like teaching operating system, re-implemented for ARMv8 (AArch64), written in C☆17Updated 4 years ago
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆233Updated 4 years ago
- A textbook on system on chip design using Arm Cortex-A☆41Updated 7 months ago
- ☆47Updated 2 weeks ago
- PCIe Device Emulation in QEMU☆87Updated 2 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated last month
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆201Updated last year
- A visual simulator for teaching computer architecture using the RISC-V instruction set☆321Updated last week
- A simple and fast RISC-V JIT emulator.☆155Updated last year
- ☆18Updated 2 years ago
- Curated list of awesome resources related with RISC-V☆94Updated 3 years ago
- Graphical-Micro-Architecture-Simulator☆119Updated 7 months ago
- QuardStar Tutorial is all you need !☆18Updated last year
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- Books☆50Updated 6 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Updated 4 years ago
- Pipelined 64-bit RISC-V core☆15Updated last year
- ☆224Updated 2 years ago
- ☆36Updated 2 weeks ago