ZaoHan415 / fxesplusLinks
Casio fx-ES PLUS reverse-engineering project
☆13Updated 7 years ago
Alternatives and similar repositories for fxesplus
Users that are interested in fxesplus are comparing it to the libraries listed below
Sorting:
- An emulator for nX-U8 based Casio fx-es PLUS calculators — maintainer notice: the most advanced fork of this repository is https://github…☆41Updated 5 years ago
- Reverse engineering of Casio fx991ex calculator QR code☆18Updated 8 years ago
- A bunch of tools I made while researching fx991es plus hacking☆52Updated 4 years ago
- An attempt to recreate the RP2040 PIO in an FPGA☆305Updated last year
- A voxel game/Minecraft clone for the iCE40 UP5K FPGA☆209Updated 4 years ago
- An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one☆53Updated 4 months ago
- What's the simplest CPU you can build?☆35Updated 11 years ago
- 8051/8052 emulator with curses-based UI☆129Updated last year
- PanoLogic Zero Client G1 reverse engineering info☆74Updated last year
- ☆64Updated last year
- "emdoom" - a port of DOOM targeted for memory-strapped systems.☆119Updated 2 years ago
- VHDL to Discrete Logic on PCB Flow☆123Updated 9 months ago
- MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD☆229Updated 7 months ago
- iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs☆38Updated 11 months ago
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆72Updated last month
- A VGA controller implemented on an AVR microcontroller.☆46Updated 12 years ago
- Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my r…☆68Updated 2 years ago
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆73Updated 2 years ago
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆45Updated last year
- ☆16Updated 8 months ago
- FPGA implementation of the Apollo Guidance Computer☆20Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 5 months ago
- A small and simple rv32i core written in Verilog☆14Updated 3 years ago
- Minimal implementation of Raybox HDL ray caster concept☆27Updated 3 months ago
- Silicon Layout Wizard☆185Updated last month
- Translation of Anlogic's FPGA datasheet, manual etc. to English.☆56Updated 6 years ago
- Design digital circuits in C. Simulate really fast with a regular compiler.☆173Updated 2 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆54Updated 4 years ago
- 2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.☆19Updated last year
- CNLohr's embedded tricks repository/readme☆105Updated 2 weeks ago