Digilent / Petalinux-Arty-Z7-20

Related projects ⓘ

Alternatives and complementary repositories for Petalinux-Arty-Z7-20

• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last month
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆43Updated 8 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 9 months ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆85Updated 5 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆72Updated 9 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆74Updated 4 years ago
• Digilent / digilent-apps
  ☆14Updated last year
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆36Updated 6 years ago
• olofk / observer
  ☆40Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆53Updated last year
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆51Updated last year
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆40Updated 6 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆112Updated 3 weeks ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆87Updated 4 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆78Updated 4 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆122Updated 9 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆24Updated 3 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆82Updated 6 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆36Updated 5 months ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆26Updated 4 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆47Updated 8 months ago