Alternatives and similar repositories for crashsheets

Users that are interested in crashsheets are comparing it to the libraries listed below

• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆35Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated 2 weeks ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated 10 months ago
• asyncvlsi / summer2022
  Summer School Week 1 & 2 repo
  ☆11Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 months ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆34Updated last month
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆68Updated 9 months ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆28Updated 4 months ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated 2 years ago
• ATaylorCEngFIET / Mastering_AMD_MicroBlaze_Processor_The_PetaLinux_Class
  ☆16Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆35Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆23Updated 6 years ago
• MicrochipTech / Libero-SoC-Design-Suite-Tcl-Examples
  Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.
  ☆10Updated 10 months ago
• robseb / HPS2FPGAmapping
  SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cycl…
  ☆38Updated 3 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆58Updated 4 years ago
• oetr / FPGA-I2C-Minion
  A simple I2C minion in VHDL
  ☆60Updated 5 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• HDLForBeginners / Examples
  ☆93Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆55Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• leonow32 / verilog-fpga
  Many peripherals in Verilog ready to use
  ☆37Updated 5 months ago
• ptracton / altera
  altera DE 0 Nano work
  ☆9Updated 10 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆22Updated 3 months ago