Alternatives and similar repositories for stm32-labs

Users that are interested in stm32-labs are comparing it to the libraries listed below

• chaseruskin / orbit
  Package manager and build system for VHDL, Verilog, and SystemVerilog
  ☆60Updated this week
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆153Updated 3 months ago
• bsc-loca / core_tile
  ☆15Updated 5 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• ilya-sotnikov / riscv-asm-spike
  Bare metal RISC-V assembly examples for Spike (no pk)
  ☆18Updated 2 years ago
• AbdelrahmanYassien11 / Verification-of-an-Asynchronous-FIFO-using-UVM-SVA
  Verification of an Asynchronous FIFO using UVM & SVA
  ☆11Updated 7 months ago
• aritramanna / 3-Wide-RISC-V-OOO-RV32-IM-Processor
  3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
  ☆22Updated 5 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆97Updated 7 months ago
• saursin / riscv-atom
  An open-source 32-bit RISC-V soft-core processor
  ☆45Updated 4 months ago
• pulp-platform / clic
  RISC-V fast interrupt controller
  ☆29Updated 2 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆200Updated last week
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆79Updated this week
• RISCV-MYTH-WORKSHOP / RISC-V-CPU-Core-using-TL-Verilog
  risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom
  ☆15Updated 5 years ago
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆143Updated last year
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆122Updated 2 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆168Updated 4 years ago
• mikinty / Hardware-Engineer-Interview-Questions
  For aspiring hardware engineers out there.
  ☆81Updated 10 months ago
• jieltan / OpenCompArchCourse
  ☆26Updated 4 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆60Updated last week
• arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
  A textbook on understanding system on chip design
  ☆59Updated 7 months ago
• iamrk-vlsi / RISC-V-MYTH-Workshop
  5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !
  ☆12Updated 3 years ago
• efabless / chipcraft---mest-course
  ☆37Updated 6 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last month
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆139Updated last month
• phoeniX-Digital-Design / phoeniX
  A Reconfigurable RISC-V Core for Approximate Computing
  ☆129Updated 8 months ago
• ecilasun / tinysys
  A tiny system built on a small QMTECH board
  ☆109Updated 9 months ago
• yavuz650 / RISC-V
  Repository for Hornet RISC-V Core
  ☆19Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆290Updated 8 months ago