Alternatives and similar repositories for vivado-docker

Users that are interested in vivado-docker are comparing it to the libraries listed below

• phwl / docker-vivado
  ☆26Updated 3 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated 2 weeks ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• tomverbeure / kv260_bringup
  Temporary repo to gather information about the Kria KV260 board
  ☆74Updated 4 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆103Updated last year
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆65Updated 2 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆91Updated last year
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• BBN-Q / vivado-docker
  Dockerfile with Vivado for CI
  ☆63Updated 8 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 4 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆80Updated last month
• filmil / vivado-docker
  Docker installation of Vivado tooling
  ☆32Updated 3 months ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆49Updated 3 weeks ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆63Updated 8 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆143Updated 8 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆73Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 5 months ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• FPGA-House-AG / BrightAI-Blackwire
  BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard
  ☆61Updated 2 years ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 10 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆114Updated last month
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated last week