Alternatives and similar repositories for pdp1-playground:

Users that are interested in pdp1-playground are comparing it to the libraries listed below

• antmicro / kenning
  ☆61Updated this week
• antmicro / warp-pipe
  ☆14Updated 4 months ago
• antmicro / renode-test-action
  GitHub Action allowing to run tests in the Renode framework
  ☆17Updated this week
• pieter3d / simview
  ☆76Updated 10 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆50Updated 11 months ago
• Wren6991 / asciiwave
  Turn WaveDrom timing diagrams into ASCII art
  ☆152Updated 11 months ago
• Gekkio / docker-fpga
  Dockerized FPGA toolchain experiments
  ☆28Updated 11 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆51Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆30Updated this week
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆109Updated 3 months ago
• toem / impulse.vscode
  impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…
  ☆29Updated 3 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• antmicro / pyrenode3
  ☆23Updated last month
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• antmicro / pyrav4l2
  Pythonic, Really Awesome V4L2 utility
  ☆20Updated 11 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆161Updated 10 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆94Updated 6 months ago
• starwaredesign / vivado-docker
  Dockerfile with Vivado for CI
  ☆12Updated 2 months ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆41Updated last month
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆78Updated last year
• im-tomu / fomu-workshop
  Support files for participating in a Fomu workshop
  ☆164Updated 10 months ago
• fjullien / migen_litex_tutorials
  ☆103Updated 2 years ago
• suoto / fpga_cores
  ☆32Updated last year
• VUnit / vunit_action
  VUnit GitHub action
  ☆15Updated 3 years ago