Alternatives and similar repositories for riscv-llvm-toolchain

Users that are interested in riscv-llvm-toolchain are comparing it to the libraries listed below

• nvdla / vp
  Virtual Platform for NVDLA
  ☆161Updated 7 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆127Updated last year
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆121Updated 4 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated this week
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆237Updated 11 months ago
• andestech / riscv-llvm
  ☆14Updated 8 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago
• plctlab / RISCV-Training
  Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.
  ☆37Updated last year
• howjmay / neon2rvv
  A translator from ARM NEON intrinsics to RISCV-V Extension implementation
  ☆41Updated 5 months ago
• umd-memsys / DRAMSim2
  DRAMSim2: A cycle accurate DRAM simulator
  ☆294Updated 5 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• Multi2Sim / multi2sim
  Multi2Sim source code
  ☆134Updated 7 years ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated last week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆97Updated last week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆206Updated last week
• riscvarchive / riscv-code-size-reduction
  ☆148Updated last year
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆285Updated this week
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆145Updated this week
• sparcians / map
  Modeling Architectural Platform
  ☆215Updated last week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆183Updated last year
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆161Updated 11 months ago
• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆161Updated 5 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆484Updated 2 months ago
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆175Updated 5 years ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆337Updated 2 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆163Updated 2 years ago
• arm-university / arm-gem5-rsk
  Official repository of the Arm Research Starter Kit on System Modeling using gem5
  ☆118Updated 7 months ago
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆236Updated last month
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 5 years ago
• riscv-non-isa / rvv-intrinsic-doc
  ☆360Updated this week