IPRC-ICT / Heron
Heron: Automatically Constrained High-Performance Library Generation for Deep Learning Accelerators
☆15Updated 9 months ago
Related projects ⓘ
Alternatives and complementary repositories for Heron
- Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators☆103Updated 2 years ago
- ☆14Updated 3 years ago
- agile hardware-software co-design☆46Updated 2 years ago
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆55Updated 7 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆74Updated last year
- EQueue Dialect☆39Updated 2 years ago
- OSDI 2023 Welder, deeplearning compiler☆16Updated 11 months ago
- MAGIS: Memory Optimization via Coordinated Graph Transformation and Scheduling for DNN (ASPLOS'24)☆43Updated 5 months ago
- STONNE Simulator integrated into SST Simulator☆17Updated 7 months ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆80Updated 6 months ago
- ☆25Updated 3 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆16Updated 2 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆28Updated 2 years ago
- ☆32Updated 2 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- DietCode Code Release☆62Updated 2 years ago
- ☆84Updated 9 months ago
- Bridging polyhedral analysis tools to the MLIR framework☆102Updated last year
- ☆15Updated 3 years ago
- ☆26Updated 3 years ago
- ☆10Updated 9 months ago
- ☆84Updated 4 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆13Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆49Updated 5 years ago
- ☆82Updated this week
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆28Updated last year
- Benchmark Framework for Buddy Projects☆46Updated 3 weeks ago