Alternatives and similar repositories for TinyZZZ

Users that are interested in TinyZZZ are comparing it to the libraries listed below

• lsleonard / tiny-data-compression
  High-speed lossless data compression of 16 to 512 bytes--get better average compression than QuickLZ for 512-byte blocks. td512 maintains…
  ☆25Updated 3 years ago
• Yongxiang-Guo / Verilog_spi_flash
  SPI通信实现FLASH读写
  ☆16Updated 5 years ago
• WangXuan95 / FPGA-SDfake
  Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。
  ☆127Updated 2 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 5 years ago
• maxs-well / USB_Ctrl
  USB2.0 Verilog
  ☆18Updated 6 years ago
• himanshu5-prog / vortexGPU
  ☆22Updated 4 years ago
• WangXuan95 / FPGA-LZMA-compressor
  An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。
  ☆87Updated 2 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• WangXuan95 / JPEG-LS_extension
  An implementation of JPEG-LS extension (ITU-T T.870).
  ☆32Updated 4 months ago
• risclite / R8051
  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
  ☆193Updated 6 years ago
• ultraembedded / core_usb_sniffer
  USB capture IP
  ☆22Updated 5 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 4 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• FlorentCLMichel / karatsuba_multiplication_verilog
  A simple implementation of the Karatsuba multiplication algorithm
  ☆11Updated 6 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆61Updated 2 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆97Updated 5 months ago
• b-dmitry1 / V188
  FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)
  ☆23Updated 3 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆51Updated 4 years ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆30Updated 5 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆19Updated 6 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆75Updated last year
• WangXuan95 / ImCvt
  A lightweight image converter which supports PNG, PNM, BMP, QOI, JPEG-LS, and H.265 intra-frame.
  ☆53Updated 4 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆33Updated last year
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 3 years ago
• merlinepedra25 / Xilinx-Unprotect
  ☆53Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆99Updated this week
• WangXuan95 / FPGA-SHA-Family
  Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。
  ☆76Updated 2 years ago