NetFPGA 1G CML Live development repository
☆14Jun 23, 2020Updated 6 years ago
Alternatives and similar repositories for NetFPGA-1G-CML-live
Users that are interested in NetFPGA-1G-CML-live are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Jul 29, 2018Updated 8 years ago
- An OpenFlow implementation for the NetFPGA-10G card☆20Feb 18, 2015Updated 11 years ago
- Try to implement GCM-AES encryption algorithm on FPGA hardware and test it by software.☆10May 31, 2019Updated 7 years ago
- ☆15Dec 19, 2025Updated 10 months ago
- TMR utilities for the SpyDrNet project☆16Nov 7, 2023Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 12 years ago
- VoHive - 4G/LTE/5G Modem Management Platform with CS Voice Bridging☆21Jul 14, 2026Updated 3 months ago
- ☆27Jun 12, 2022Updated 4 years ago
- Comprehensive management and proxy service platform for Qualcomm 4G/LTE/5G modules (Quectel EC20/EC25/EC21/EG25/EM20, etc.). keyword: voh…☆24Jul 21, 2026Updated 3 months ago
- Hardware Architecture for 30fps Full-HD Guided Image Filter☆12Jul 20, 2019Updated 7 years ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- IPASS -- Image Processing Algorithm Simulation Software☆12Jul 25, 2025Updated last year
- Memory Compiler Tutorial☆15Oct 7, 2020Updated 6 years ago
- SGMII☆14Jul 17, 2014Updated 12 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 电影订票购票管理系统-毕业设计☆10Nov 15, 2023Updated 2 years ago
- verilog实现CLAHE（限制对比度自适应直方图均衡化）算法，并进行资源优化，含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆21Apr 30, 2026Updated 6 months ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆22Sep 11, 2026Updated last month
- ☆15May 10, 2016Updated 10 years ago
- Ethernet switch implementation written in Verilog☆66Jun 13, 2023Updated 3 years ago
- ☆15Jun 1, 2019Updated 7 years ago
- IEEE P1735 decryptor for VHDL☆42Jun 23, 2015Updated 11 years ago
- A database of concentrating solar power plants of the world for energy modellers and analysts.☆20Oct 7, 2025Updated last year
- ☆10Aug 28, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆18Mar 30, 2025Updated last year
- 3DNR proccessing using Halide☆15Nov 22, 2021Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆60Oct 18, 2023Updated 3 years ago
- ☆14Jun 6, 2023Updated 3 years ago
- ☆11Mar 30, 2022Updated 4 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆47Nov 24, 2014Updated 11 years ago
- Verilog Implementation of Otsu's algorithm☆14Jan 18, 2020Updated 6 years ago
- LiteX-based gateware for LimeSDR boards.☆22Oct 20, 2026Updated last week
- Test scripts for traffic light detection and classification☆11Oct 12, 2017Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Netcope P4 Examples☆13Jan 7, 2020Updated 6 years ago
- SystemVerilog Example Files☆11Jan 15, 2013Updated 13 years ago
- iSCSI Target Daemon for Linux/Windows for sharing SCSI (real & virtual, like SATA) devices☆20Oct 11, 2013Updated 13 years ago
- ☆17Apr 7, 2026Updated 6 months ago
- IR image processing and demo on a Zybo Z7-20 using a Raspberry Pi night vision vamera☆14Aug 30, 2021Updated 5 years ago
- This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface.…☆22Oct 28, 2024Updated 2 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago