无名创新开源遥控器
☆17Sep 20, 2020Updated 5 years ago
Alternatives and similar repositories for HGS_HP
Users that are interested in HGS_HP are comparing it to the libraries listed below
Sorting:
- 利用扩展卡尔曼滤波进行姿态解算☆14Dec 8, 2015Updated 10 years ago
- 智能手环,穿戴式设备☆12May 16, 2016Updated 9 years ago
- ☆11May 31, 2016Updated 9 years ago
- Modified according to Smoothieboard v1.1 5driver, more compact and cost-effective design.☆33Jul 3, 2023Updated 2 years ago
- Multipurpose GUI/Datalogger software for ground station with real time plotting up to 8 sensors.☆11Nov 10, 2023Updated 2 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- 基于STM-32的智能循迹避障小车☆11Jul 4, 2018Updated 7 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- ☆13Apr 14, 2023Updated 2 years ago
- 自己学习 Qt QCustomPlot库的例程☆12Oct 18, 2020Updated 5 years ago
- 无名科创开源飞控群:540707961☆224Jan 16, 2024Updated 2 years ago
- 惯导/GPS 组合导航相关☆47Mar 26, 2019Updated 6 years ago
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 3 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- 使用verilog编写sdram控制器☆12Jun 22, 2019Updated 6 years ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- Qt串口调试工具☆10Jul 19, 2017Updated 8 years ago
- OneWire library custom engineered for JLD505 boards with DS2480B chips☆11Jul 1, 2015Updated 10 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- An arduino based remote controlled airplane with PID control loop using MPU6050☆15Sep 22, 2019Updated 6 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Oct 3, 2017Updated 8 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- ☆10Aug 15, 2019Updated 6 years ago
- 200W 铝基板加热台控制器,具备PID控制,PWM输出,卡尔曼滤波☆11Oct 30, 2022Updated 3 years ago
- A C library for using an MPR121-based touch sensor with the Raspberry Pi Pico☆11Dec 6, 2023Updated 2 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 8 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- 一个开源的基于stm32的磁悬浮项目☆15Nov 21, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- 基于Vue.js和SpringBoot的流浪动物管理系统,分为用户前台和管理后台,可以给管理员、普通用户角色使用,包括宠物管理模块、宠物领养模块、宠物寄养模块、论坛管理模块、公告信息模块☆15Aug 8, 2024Updated last year
- 基于STM32G0/STM32F0的手腕控制无按键手环☆39Jun 18, 2022Updated 3 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- [JSP] 终点小说网:JSP课程设计,简单的登录注册、数据库、MVC、抓包、发布作品等☆11Feb 27, 2019Updated 7 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- [QT] 随机抽奖转盘(重写他人)☆10Feb 27, 2019Updated 7 years ago
- I just wanted to try to do it myself. No more updates for the moment as the firmware is now too big for the radio's memory.☆10Jan 15, 2024Updated 2 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- GPS&BD2卫星导航系统模拟信号源☆11Aug 6, 2015Updated 10 years ago