Alternatives and similar repositories for XSOC-xr16

Users that are interested in XSOC-xr16 are comparing it to the libraries listed below

• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆54Updated 4 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated 2 years ago
• PythonLinks / awesome-risc-v-soft-cores
  Compares the different RISC-V soft cores in order to help you select the best one for your application.
  ☆13Updated 6 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last month
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 10 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆87Updated 6 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆14Updated 4 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆61Updated last week
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆21Updated 8 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆56Updated 5 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆30Updated last week
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 4 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆47Updated 4 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆18Updated 3 years ago
• fiberhood / MorphleLogic
  Morphle Logic V1.0, an open hardware asynchronous runtime reconfigurable array ARRA or PPL,FPGA,CPLD
  ☆23Updated 2 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆74Updated this week
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆19Updated 2 years ago
• howerj / lfsr-vhdl
  An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one
  ☆53Updated 6 months ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 6 years ago
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 7 months ago
• AngelTerrones / Algol
  A RISC-V CPU (Outdated: using priviledge v1.7)
  ☆26Updated 6 years ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆13Updated 9 years ago