synflow / ngDesign
☆16Updated this week
Related projects: ⓘ
- A pipelined RISCV implementation in VHDL☆95Updated 5 years ago
- ☆46Updated 8 years ago
- Spacecraft Multicore Emulator Based on Leon 3 Sparc V8 architecture processor☆49Updated 5 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆59Updated 4 years ago
- ☆122Updated this week
- An open source miniPCIe development board based on the Xilinx Spartan 6 LX150T☆141Updated 8 years ago
- Epiphany SDK build scripts (start here!)☆125Updated 4 years ago
- Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH☆28Updated 9 years ago
- Simple examples showing how to program the Epiphany☆85Updated 4 years ago
- Library of various community contributed Parallella board admin scripts and programs☆39Updated 7 years ago
- Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture☆62Updated last year
- Linux Kernel forked from ADI (with latest ADI HDMI drivers)☆68Updated 5 years ago
- ☆234Updated this week
- A (Py)thon (D)SL for (G)enerating (In)struction set simulators.☆165Updated 6 years ago
- Official U-Boot package for Parallella☆41Updated 9 years ago
- a simple C-to-Verilog compiler☆47Updated 7 years ago
- ☆29Updated this week
- An executable specification of the RISCV ISA in L3.☆41Updated 5 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 4 years ago
- Source code form the Parallella Chronicles Blog☆15Updated 9 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆55Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆45Updated 7 years ago
- GCC for Epiphany☆16Updated 5 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆38Updated 8 years ago
- BSP implementation for the Parallella; the world's smallest supercomputer☆27Updated 7 years ago
- How To Retarget the GNU Toolchain in 21 Patches☆82Updated 9 years ago
- FPGA Design Suite based on C to Verilog design flow.☆230Updated 5 years ago
- The CO-PRocessing THReads (COPRTHR) SDK - latest release is v1.6.2 (Freewill)☆94Updated 8 years ago
- An exercise in cryptographic minimlism☆24Updated 9 years ago
- My fork of the buildroot system☆17Updated 9 years ago