Alternatives and similar repositories for eth-computer-architecture

Users that are interested in eth-computer-architecture are comparing it to the libraries listed below

• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆29Updated 4 years ago
• aniketp / ipcp-dsp
  Instruction Pointer Classifier and Dynamic Degree Stream based Hardware Cache Prefetching
  ☆16Updated 5 years ago
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 4 years ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆27Updated last year
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆29Updated 5 years ago
• EricJin2002 / UCAS-CA-2022
  一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块
  ☆15Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆85Updated 5 years ago
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆51Updated 3 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆143Updated last year
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆13Updated 2 weeks ago
• Corle-hyz / UCAS-COD-Lab
  中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业
  ☆16Updated 3 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆65Updated 3 years ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆12Updated 4 years ago
• kyaso / py-v
  A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.
  ☆17Updated 3 weeks ago
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆39Updated 3 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• RealJustinNi / EE219-AICS-2024
  ☆15Updated 8 months ago
• FanQinFred / Cache
  重庆大学计算机学院2018级计算机体系结构cache设计
  ☆11Updated 4 years ago
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆20Updated 6 years ago
• USTC-System-Courses / CECS-Lab
  ☆40Updated last year
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆17Updated 5 months ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆23Updated 8 months ago
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆22Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• OSCPU / yosys-sta
  ☆81Updated 4 months ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆16Updated last year
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆32Updated 2 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago