RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
☆105Jul 30, 2022Updated 4 years ago
Alternatives and similar repositories for riscv-disassembler
Users that are interested in riscv-disassembler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Proof-of-concept implementation for the paper "Reviving Meltdown 3a" (ESORICS 2023)☆17Sep 25, 2023Updated 3 years ago
- RISC-V Instruction Set Metadata☆43Oct 21, 2018Updated 8 years ago
- RISC-V simulator for x86-64☆727Feb 5, 2022Updated 4 years ago
- Linux kernel build scripts and patches for Fedora/RISC-V☆16Nov 8, 2018Updated 8 years ago
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆20Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- tldr file for riscv assembly instructions☆18Feb 28, 2021Updated 5 years ago
- Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…☆29Nov 30, 2023Updated 2 years ago
- The AcornOS kernel.☆14Sep 15, 2023Updated 3 years ago
- A very simple RISC-V ISA emulator.☆40Dec 12, 2020Updated 5 years ago
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Jan 26, 2020Updated 6 years ago
- A minimal RISC-V RV32I disassembler☆56Jun 15, 2021Updated 5 years ago
- LLVM for the Apollo Guidance Computer☆10Jan 28, 2019Updated 7 years ago
- ☆22Nov 3, 2025Updated last year
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Tool for automated testing and analysis of Intel x86-64 undocumented instructions in user mode and in the kernel☆48May 10, 2019Updated 7 years ago
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆809Updated this week
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆77Mar 31, 2018Updated 8 years ago
- Porting LuaJIT to RISC-V 64☆35Aug 11, 2026Updated 2 months ago
- Binsec/Haunted is an extension of Binsec to verify speculative constant-time and detect Spectre attacks.☆18Oct 19, 2023Updated 3 years ago
- ☆34Jul 22, 2020Updated 6 years ago
- Run SPEC CPU2006 on Linux with either an Intel, ARM, or PowerPC processors.☆29Apr 25, 2018Updated 8 years ago
- Learning Verilog using IceStudio ( Board IceStick )☆11Jan 12, 2022Updated 4 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RISC-V Assembly Programmer's Manual☆1,661Oct 19, 2026Updated 3 weeks ago
- Environment for DynoRoot (CVE-2018-1111)☆13May 17, 2018Updated 8 years ago
- Dual-Core Out-of-Order MIPS CPU Design☆26May 8, 2025Updated last year
- RISC-V Processor Tracing tools and library☆15Mar 17, 2024Updated 2 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆114Sep 18, 2021Updated 5 years ago
- A (Miasm2 + binaryninja) based function divination.☆15Oct 22, 2017Updated 9 years ago
- RISC-V Opcodes☆888Oct 14, 2026Updated 3 weeks ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆34May 20, 2026Updated 5 months ago
- Rust-based compiler for the Address Language developed by Kateryna Logvynivna Yushchenko.☆15Jan 24, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A near gate-level Verilog simulation of the 6502 microprocessor.☆23Dec 25, 2024Updated last year
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- Weekly RISC-V Newsletter☆28Nov 29, 2018Updated 7 years ago
- Core Lightning plugin for sending zap (NIP-57) notes☆10Aug 22, 2023Updated 3 years ago
- X86 disassembler benchmark☆76Oct 26, 2025Updated last year
- Instruction Set Generator initially contributed by Futurewei☆323Oct 17, 2023Updated 3 years ago
- Win32 HLE emulator thing☆11Mar 29, 2022Updated 4 years ago
Are these results useful?