《互联网络原理与实践(中文翻译)》Principles and Practices of Interconnection Networks
☆32Nov 20, 2020Updated 5 years ago
Alternatives and similar repositories for Principles-and-Practices-of-Interconnection-Networks--Chinese
Users that are interested in Principles-and-Practices-of-Interconnection-Networks--Chinese are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TACOS: [T]opology-[A]ware [Co]llective Algorithm [S]ynthesizer for Distributed Machine Learning☆37Jun 13, 2025Updated last year
- BookSim 1.0☆27Mar 22, 2014Updated 12 years ago
- A sample kernel module showing the memory reordering.☆13May 30, 2020Updated 6 years ago
- ☆13Mar 18, 2024Updated 2 years ago
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Project repo for the POSH on-chip network generator☆53Mar 18, 2025Updated last year
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- ☆11Mar 15, 2023Updated 3 years ago
- ☆10Aug 2, 2021Updated 5 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- Projects for the Scarab Minispartan6+ FPGA board☆14Jun 20, 2015Updated 11 years ago
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- SystemVerilog implemention of the TAGE branch predictor☆14May 26, 2021Updated 5 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆30Sep 16, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A high-throughput and memory-efficient inference and serving engine for LLMs☆16Jul 19, 2026Updated last month
- ☆14Dec 20, 2024Updated last year
- AFPQ code implementation☆23Nov 6, 2023Updated 2 years ago
- ☆14Jan 10, 2023Updated 3 years ago
- Code for DCT_SNN, an input encoding scheme for SNNs using DCT☆21Sep 30, 2021Updated 4 years ago
- Rebuilding ...☆11Apr 20, 2021Updated 5 years ago
- Parallel implementation of Graph Convolutional Networks on CPU☆17Jul 3, 2019Updated 7 years ago
- Unofficial pytorch implementation of Piecewise Linear Unit dynamic activation function☆18Feb 8, 2023Updated 3 years ago
- a screen snapshot application under UEFI☆10Jan 22, 2014Updated 12 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Just do a 'micro' work.☆21May 28, 2022Updated 4 years ago
- ☆19Aug 22, 2022Updated 4 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆21Updated this week
- Linux Kernel Learning☆13Jan 20, 2017Updated 9 years ago
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Oct 11, 2017Updated 8 years ago
- ☆16Aug 20, 2024Updated 2 years ago
- Network on Chip Simulator☆332Jun 9, 2026Updated 2 months ago
- Source code for Multifidielity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures☆30Jan 29, 2026Updated 7 months ago
- Parallel_Computer_Architecture经典书籍☆17May 13, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆17Jul 31, 2024Updated 2 years ago
- A simple implementation of locality sensitive hashing in python☆25Feb 4, 2017Updated 9 years ago
- A Python/C++ implementation of Quine McCluskey(Tabulation) method.☆12Aug 31, 2018Updated 7 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- ☆246Jun 25, 2025Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆27Aug 23, 2021Updated 5 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆21May 30, 2023Updated 3 years ago