《互联网络原理与实践(中文翻译)》Principles and Practices of Interconnection Networks
☆28Nov 20, 2020Updated 5 years ago
Alternatives and similar repositories for Principles-and-Practices-of-Interconnection-Networks--Chinese
Users that are interested in Principles-and-Practices-of-Interconnection-Networks--Chinese are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TACOS: [T]opology-[A]ware [Co]llective Algorithm [S]ynthesizer for Distributed Machine Learning☆32Jun 13, 2025Updated 9 months ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- Code for DCT_SNN, an input encoding scheme for SNNs using DCT☆20Sep 30, 2021Updated 4 years ago
- GPU-accelerated LLM Training Simulator☆18Jun 26, 2025Updated 9 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆23Jun 11, 2025Updated 9 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Nov 12, 2025Updated 4 months ago
- Just do a 'micro' work.☆20May 28, 2022Updated 3 years ago
- A Python/C++ implementation of Quine McCluskey(Tabulation) method.☆11Aug 31, 2018Updated 7 years ago
- Tutorial Material from the SST Team☆25Aug 5, 2025Updated 7 months ago
- The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate …☆31Updated this week
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆40Feb 23, 2026Updated last month
- ☆22Nov 3, 2025Updated 4 months ago
- rv8 benchmark suite☆25Jul 30, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- RISC-V IOMMU Demo (Linux & Bao)☆24Dec 5, 2023Updated 2 years ago
- ESP32 + MLX90640 IR Camera using the native ESP-IDF☆10Mar 28, 2020Updated 5 years ago
- ☆15May 22, 2024Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Aug 23, 2021Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆227Nov 7, 2025Updated 4 months ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 2 years ago
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆38Mar 7, 2026Updated 2 weeks ago
- Demo host and enclave applications exercising most functionality.☆32Jun 12, 2023Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Mar 19, 2026Updated last week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Network on Chip Simulator☆307Oct 26, 2025Updated 5 months ago
- ☆38Jun 3, 2024Updated last year
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 3 years ago
- Share short notes with just a link. No database. No storage!☆19Sep 18, 2025Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Mar 11, 2026Updated 2 weeks ago
- The wafer-native AI accelerator simulation platform and inference engine.☆52Jan 1, 2026Updated 2 months ago
- This is a tutorial to learn LLVM, I realize a backend to compiler machine code for cpu0 which is a simple RISC cpu.☆271Dec 28, 2021Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Jul 5, 2025Updated 8 months ago
- BookSim 1.0☆25Mar 22, 2014Updated 12 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- RISC-V Security Model☆34Updated this week
- ☆12Mar 1, 2021Updated 5 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Apr 3, 2024Updated last year
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated last month
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆47Oct 14, 2022Updated 3 years ago
- ☆32Aug 21, 2021Updated 4 years ago
- Cheapest UAC2 using STM32F407+USB3300☆21Feb 26, 2025Updated last year