Alternatives and similar repositories for ttihp-verilog-template

Users that are interested in ttihp-verilog-template are comparing it to the libraries listed below

• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆74Updated this week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆86Updated 10 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 2 months ago
• olofk / corescore
  CoreScore
  ☆166Updated 2 weeks ago
• mineda-support / ICPS2023_5
  ☆57Updated 3 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last week
• olofk / qerv
  ☆18Updated 6 months ago
• ecilasun / tinysys
  A tiny system built on a small QMTECH board
  ☆109Updated 7 months ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆72Updated 3 weeks ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆116Updated this week
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆33Updated 10 months ago
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆27Updated last week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• adonairc / tt07-dda-van-der-pol
  DDA solver for the van der Pol oscillator using 16-bit posits
  ☆28Updated 9 months ago
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆22Updated 11 months ago
• TinyTapeout / tt-multiplexer
  ☆18Updated last month
• machdyne / kuchen
  Kuchen Computer
  ☆23Updated last year
• TinyTapeout / tt07-verilog-template
  Submission template for Tiny Tapeout 7 - Verilog HDL Projects
  ☆21Updated last year
• efabless / clear
  ☆71Updated last year
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆17Updated 4 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 6 months ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆153Updated last week
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆32Updated last year
• TinyTapeout / tt10-verilog-template
  Submission template for Tiny Tapeout 10 - Verilog HDL Projects
  ☆25Updated 4 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆84Updated this week
• TinyTapeout / tinytapeout-06
  Tiny Tapeout 06
  ☆14Updated last month
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆186Updated last month