Alternatives and similar repositories for ttihp-verilog-template

Users that are interested in ttihp-verilog-template are comparing it to the libraries listed below

• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆90Updated 11 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆74Updated this week
• TinyTapeout / tinytapeout-06
  Tiny Tapeout 06
  ☆15Updated 2 weeks ago
• TinyTapeout / tt-support-tools
  Tiny Tapeout project build tools + chip integration scripts
  ☆28Updated this week
• TinyTapeout / tt-multiplexer
  ☆19Updated this week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆33Updated 10 months ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆139Updated 2 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆75Updated this week
• efabless / clear
  ☆71Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 2 weeks ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• mineda-support / ICPS2023_5
  ☆57Updated 4 months ago
• TinyTapeout / tt07-verilog-template
  Submission template for Tiny Tapeout 7 - Verilog HDL Projects
  ☆21Updated last year
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆154Updated this week
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆18Updated 4 years ago
• TinyTapeout / tt10-verilog-template
  Submission template for Tiny Tapeout 10 - Verilog HDL Projects
  ☆25Updated 5 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• olofk / corescore
  CoreScore
  ☆168Updated 2 weeks ago
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆189Updated 2 months ago
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆23Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆30Updated 2 weeks ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆58Updated 2 weeks ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆121Updated 3 months ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆62Updated 7 months ago
• siliconcompiler / scgallery
  SiliconCompiler Design Gallery
  ☆52Updated this week
• olofk / qerv
  ☆18Updated 6 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆81Updated last month