skiphansen / panog2_linux
Prebuilt images for Linux for the Pano Logic G2
☆12Updated last year
Related projects: ⓘ
- Network based loader and flasher for Pano G2 devices☆13Updated last year
- A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client☆33Updated 5 years ago
- Flashing Pano Logic thin clients without a programmer☆38Updated 2 years ago
- Port of Brian Bennet's NES Emulator for the second generation Panologic thin client☆11Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated last year
- How to use the Intel JTAG primitive without using virtual JTAG☆16Updated 2 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆34Updated last year
- ☆11Updated last month
- Minimig project example for FleaFPGA Ohm Experimenter Board☆24Updated 2 years ago
- Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K☆20Updated 2 years ago
- An FPGA/PCI Device Reference Platform☆29Updated 3 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆25Updated 3 years ago
- Retro Z80 computer for the Pano Logic Thin Client☆45Updated 2 years ago
- FPGA based PDP-11 cpu☆17Updated 8 years ago
- A highly-configurable and compact variant of the ZPU processor core☆34Updated 9 years ago
- Mostly AVR compatible FPGA soft-core☆24Updated 2 years ago
- Test of a RP2040 PMOD attached to a LiteX SoC.☆23Updated last year
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆19Updated 10 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Updated 4 years ago
- ISA card expansion for LPC and Glasgow☆10Updated 5 years ago
- Z80 CPU + UART + Timer + I/O Ports coded in VHDL and implemented for the Lattice iCE40-hx8k dev board☆8Updated 8 years ago
- Misc iCE40 specific cores☆14Updated last year
- Simple 6502 system on a ULX3S FPGA board☆16Updated 4 years ago
- RCA COSMAC CDP1802 functional equivalent CPU core in VHDL☆25Updated 6 years ago
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆26Updated 5 years ago
- nMigen examples for the ULX3S board☆15Updated 3 years ago
- simple sdram controller☆17Updated 3 years ago
- XC2064 bitstream documentation☆16Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆41Updated 5 years ago
- Smol 2-stage RISC-V processor in nMigen☆23Updated 3 years ago