kevinwlu / dsdLinks
Digital System Design
☆42Updated last week
Alternatives and similar repositories for dsd
Users that are interested in dsd are comparing it to the libraries listed below
Sorting:
- RISC-V Nox core☆64Updated 2 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 6 months ago
- Simple 8-bit UART realization on Verilog HDL.☆105Updated last year
- A simple three-stage RISC-V CPU☆23Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- Simple implementation of I2C interface written on Verilog and SystemC☆42Updated 7 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 3 weeks ago
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆66Updated last month
- Open source ISS and logic RISC-V 32 bit project☆53Updated this week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- A reference book on System-on-Chip Design☆29Updated last year
- ☆42Updated 7 months ago
- ☆59Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- ☆35Updated 6 months ago
- System Verilog BootCamp☆24Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆93Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- ☆32Updated 7 months ago
- 64-bit multicore Linux-capable RISC-V processor☆93Updated last month
- ☆24Updated 3 weeks ago