kevinwlu / dsdLinks
Digital System Design
☆47Updated this week
Alternatives and similar repositories for dsd
Users that are interested in dsd are comparing it to the libraries listed below
Sorting:
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆61Updated 5 years ago
- Simple 8-bit UART realization on Verilog HDL.☆114Updated last year
- Implemetation of pipelined ARM7TDMI processor in Verilog☆94Updated 7 years ago
- 📦 Prebuilt RISC-V GCC toolchains for x64 Linux.☆107Updated 11 months ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆25Updated 3 years ago
- A simple three-stage RISC-V CPU☆25Updated 4 years ago
- RISCV CPU implementation in SystemVerilog☆32Updated 4 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- Open source ISS and logic RISC-V 32 bit project☆60Updated 2 weeks ago
- Dual-Core Out-of-Order MIPS CPU Design☆19Updated 8 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 months ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 9 months ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- Verilog package manager written in Rust☆144Updated last year
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆40Updated 2 years ago
- Arduino compatible Risc-V Based SOC☆160Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- Submission template for Tiny Tapeout 6 - Verilog HDL Projects☆35Updated last year
- Another tiny RISC-V implementation☆64Updated 4 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆76Updated 2 years ago
- ☆60Updated 4 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- OpenSPARC-based SoC☆75Updated 11 years ago
- An Open Source Link Protocol and Controller☆28Updated 4 years ago