kevinwlu / dsdLinks
Digital System Design
☆45Updated this week
Alternatives and similar repositories for dsd
Users that are interested in dsd are comparing it to the libraries listed below
Sorting:
- VHDL extension for visual studio code☆20Updated 6 months ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- 📦 Prebuilt RISC-V GCC toolchains for x64 Linux.☆106Updated 7 months ago
- Arduino compatible Risc-V Based SOC☆156Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.☆45Updated 11 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆83Updated this week
- A series of CORDIC related projects☆115Updated 11 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 11 months ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- Python Model of the RISC-V ISA☆56Updated 3 years ago
- DisplayPort IP-core☆78Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- Another tiny RISC-V implementation☆59Updated 4 years ago
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆36Updated 2 years ago
- Verilog package manager written in Rust☆143Updated last year
- OpenSPARC-based SoC☆70Updated 11 years ago
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- An open source CPU design and verification platform for academia☆111Updated last month
- FPGA implementation of the 8051 Microcontroller (Verilog)☆50Updated 11 years ago
- A simple three-stage RISC-V CPU☆24Updated 4 years ago
- Linux capable RISC-V SoC designed to be readable and useful.☆152Updated 4 months ago
- Many peripherals in Verilog ready to use☆39Updated 9 months ago
- VHDL Implementation of AES Algorithm☆86Updated 4 years ago
- Simple RiscV core for academic purpose.☆22Updated 5 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆64Updated 11 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 11 months ago