SystemOT, yet another home brew cpu.
☆25Aug 9, 2022Updated 3 years ago
Alternatives and similar repositories for Home-Brew-Computer
Users that are interested in Home-Brew-Computer are comparing it to the libraries listed below
Sorting:
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- ☆12Aug 12, 2022Updated 3 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- 经典的嵌入式OS - ucos-II 2.52版本全注释，仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- ☆13Aug 7, 2025Updated 6 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆13Sep 5, 2023Updated 2 years ago
- compresses and encrypts your Backup dirs and stores them onto a Tape drive with email notification for manual tape swap needed☆11Jun 15, 2022Updated 3 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆15Feb 16, 2026Updated last week
- livecoding talk for oscon 2018☆10Jul 18, 2018Updated 7 years ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- This is DreamOS C Version by lizhirui since 2021-05-18☆10Aug 23, 2021Updated 4 years ago
- Nintendo Switch port of "The Powder Toy"☆12Sep 25, 2019Updated 6 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- ☆13May 8, 2025Updated 9 months ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- Source code for PDP-9 SPACEWAR! binary found at Dartmouth College in the early 1970s☆11Jun 14, 2020Updated 5 years ago
- A simple CPU implemented by discrete CPLD components.☆13Jul 12, 2023Updated 2 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- Arch Linux ARM for Xilinx Zynq UltraScale+ devices☆13Jul 21, 2024Updated last year
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Jan 17, 2024Updated 2 years ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- simple 4-BIT CPU with 74-serials chip，origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- ☆12Apr 27, 2017Updated 8 years ago
- Deep learning algorithms developed by ourselves from scratch by C++. No deep learning frameworks are used.☆10Aug 3, 2020Updated 5 years ago
- Stuff one needs to play around with my R316 computers (see README)☆15Feb 12, 2026Updated 2 weeks ago
- ☆12Feb 20, 2026Updated last week
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Simian Process Oriented Conservative JIT PDES from LANL☆13Dec 12, 2025Updated 2 months ago
- ☆15Dec 17, 2025Updated 2 months ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated last year
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 2 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago