daily_fudan的运行器，自动定时执行https://github.com/Limour-dev/daily_fudan_core 的代码。请按daily_fudan_core的readme正确配置FUDAN，按本仓库的readme正确配置GH_PAT。两个secrets都在本仓库配置，注意不要配置到core仓库。
☆26Dec 14, 2022Updated 3 years ago
Alternatives and similar repositories for daily_fudan_actions
Users that are interested in daily_fudan_actions are comparing it to the libraries listed below
Sorting:
- ☆11May 31, 2016Updated 9 years ago
- A bot that automatically adds commits to your private repository to give your profile a boost in terms of contribution☆10Jul 14, 2021Updated 4 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Algorithms notes learning from ZuoShen.☆10Jun 30, 2022Updated 3 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- Script to sync Google Forms to Fusion Tables, updated from Google's version☆10Dec 17, 2014Updated 11 years ago
- 一个开源的基于stm32的磁悬浮项目☆15Nov 21, 2023Updated 2 years ago
- An Accelerator for Convolution layer designed with Vivado HLS.☆10Dec 4, 2020Updated 5 years ago
- ☆11Jan 15, 2021Updated 5 years ago
- Utilities for printing to Brother PTouch PT-P750W☆10Feb 1, 2026Updated last month
- Contract Code for the NotSafeMoon Token on The Binance Smart Chain at address 0x337e35Ed5B38D5C7Ec9F8d7cF78fe7F43d7DEC6F☆10May 4, 2021Updated 4 years ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- 200W 铝基板加热台控制器，具备PID控制，PWM输出，卡尔曼滤波☆11Oct 30, 2022Updated 3 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 8 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Oct 3, 2017Updated 8 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- ☆10Aug 15, 2019Updated 6 years ago
- 使用verilog编写sdram控制器☆12Jun 22, 2019Updated 6 years ago
- Appraisal and analytics website for NFTs on Binance Smart Chain☆11Nov 8, 2021Updated 4 years ago
- Meet Me .! Misbah Ur Rahman. Selftaught individual who speaks 0's & 1s. Mixture of passsion and profession. Be my guest let's discuss any…☆10Dec 5, 2024Updated last year
- Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- GPS&BD2卫星导航系统模拟信号源☆11Aug 6, 2015Updated 10 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- Handshake integration with Coinbase Rosetta☆13Mar 26, 2022Updated 3 years ago
- 仿Coinbase数字货币交易应用☆13Dec 11, 2017Updated 8 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- Solver for 1D nonlinear partial differential equations in Julia based on the collocation method of Skeel and Berzins and providing an API…☆15Aug 5, 2024Updated last year
- ☆14Jun 30, 2019Updated 6 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- 一个小型操作系统的学习与实现☆10Feb 18, 2021Updated 5 years ago
- QR Code Generator for Titanium Mobile☆27Jan 14, 2019Updated 7 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- ☆13Apr 1, 2017Updated 8 years ago