Alternatives and similar repositories for Lunion

Users that are interested in Lunion are comparing it to the libraries listed below

• jdcneto / Lung-Sound-Classification
  This project is about classifying respiratory sounds using Attention and Vision Transformer on ICBHI dataset..
  ☆19Updated last year
• rannilo / respiratory-disease-prediction
  This codebase is focused on predicting lung diseases from a breathing sounds dataset. 8 experiments were conducted on 5 different machine…
  ☆11Updated 4 years ago
• AlexKly / Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex
  Voice Activity Detector based on MFCC features and DNN model
  ☆26Updated 2 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆13Updated 4 years ago
• aakashvenky / ECG-signal-processing-using-ModelSim
  ECG signals acquired using a sensor has a lot of noise due to lung sounds and EMG. The noise due to lung sounds, EMG can be removed by us…
  ☆13Updated 5 years ago
• SJTU-YONGFU-RESEARCH-GRP / Lung-Sound-Classification-System-LungSys-I
  PyTorch, Android application code for lung sound classification
  ☆23Updated 5 years ago
• suburaaj / Fpga-Implementation-of-Precise-Convolutional-Neural-Network-for-Extreme-Learning-Machine
  Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…
  ☆12Updated 5 years ago
• linxiaobo110 / rps_u96
  ☆12Updated 5 years ago
• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆15Updated 4 years ago
• elliothe / N3H_Core
  [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores
  ☆12Updated 3 years ago
• niexun / LSTM
  LSTM neural network (verilog)
  ☆15Updated 6 years ago
• Zyy438 / FPGAudio
  A set of audio processing functions implemented by FPGA
  ☆29Updated 4 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• Charmve / AccANN
  🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
  ☆20Updated last year
• pulp-platform / fann-on-mcu
  ☆31Updated 5 years ago
• IA-C-Lab-Fudan / KWS-SoC
  This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
  ☆53Updated 5 years ago
• cam-mobsys / covid19-sounds-neurips
  COVID19 Sounds Dataset Supplementary Material
  ☆19Updated 3 years ago
• chumingqian / Deploy_Yolov4_On_Ultra96_v2
  Model deployment, Yolov4, xilinx, Ultra96_v2.
  ☆15Updated 3 years ago
• VGuoGavin / Hand-Writing-Digital-Recognization-Based-on-FPGA
  Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…
  ☆13Updated 2 years ago
• AILearnerLi / DAC-SDC-2020-SEUer
  ☆26Updated 2 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆26Updated 3 years ago
• Elrori / FMCW_Radar
  FMCW Radar verilog project
  ☆32Updated 5 years ago
• zhengchen3 / HLS_Transformer
  c++ version of ViT
  ☆12Updated 2 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆29Updated 2 years ago
• sritanmotati / lung-sound-classification
  Diagnosing respiratory diseases using sounds of respiratory cycles.
  ☆18Updated 3 years ago
• EEESlab / CMSIS_NN-INTQ
  INT-Q Extension of the CMSIS-NN library for ARM Cortex-M target
  ☆18Updated 5 years ago
• yportne13 / spinalAdderNetMNIST
  SpinalHDL AdderNet MNIST
  ☆11Updated 4 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆10Updated 2 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆31Updated 5 years ago