开源国密SM2/SM3/SM4算法，基于GmSSL，基于OpenSSL1.1.0
☆12Apr 22, 2017Updated 9 years ago
Alternatives and similar repositories for opensm
Users that are interested in opensm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [Qt工具] 字符串加密工具，有 AES、Base64+XOR 两种。☆11Jul 15, 2019Updated 7 years ago
- Automatically exported from code.google.com/p/xml2rfc-xxe☆12Jul 9, 2022Updated 4 years ago
- Algorand's reference implementation of bls signature scheme☆14Sep 7, 2020Updated 6 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆15Jul 5, 2020Updated 6 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Memory Controller IP Core☆10Jul 17, 2014Updated 12 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- a MIPS-based embedded system on FPGA☆10Mar 10, 2017Updated 9 years ago
- ☆13Sep 8, 2017Updated 9 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆16Oct 1, 2019Updated 7 years ago
- ☆14Aug 26, 2016Updated 10 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- R package to fit LDA topic models (deprecated)☆20Aug 14, 2015Updated 11 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 10 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- Gibbs sampling inference to LDA☆19Apr 4, 2014Updated 12 years ago
- unsigned Radix-2 SRT division,基2除法☆17May 12, 2015Updated 11 years ago
- The .NET data provider for GaussDB.☆12Jun 22, 2026Updated 3 months ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Sep 21, 2026Updated 3 weeks ago
- A collection of collected RSSAC002 data☆15Oct 7, 2026Updated last week
- ☆16Mar 18, 2024Updated 2 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆15Mar 10, 2019Updated 7 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- 4096bit Iterative digit-digit Montgomery Multiplication in Verilog☆20Apr 18, 2022Updated 4 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- ☆11Jul 14, 2015Updated 11 years ago
- My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University☆12May 14, 2017Updated 9 years ago
- learning VHDL☆13Jul 1, 2014Updated 12 years ago