Alternatives and similar repositories for tt-bh-linux

Users that are interested in tt-bh-linux are comparing it to the libraries listed below

• charlottia / hdx
  HDL development environment on Nix.
  ☆26Updated last year
• dsheffie / rv64core
  ☆13Updated this week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆93Updated last week
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆63Updated 2 weeks ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 8 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• tenstorrent / tt-umd
  User-Mode Driver for Tenstorrent hardware
  ☆36Updated this week
• benpye / nix-fpga-tools
  ☆27Updated 3 years ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated last week
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆33Updated last year
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated last month
• hrw / arm-socs-table
  Table of ARM SoC and their features
  ☆61Updated last month
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• antmicro / rdimm-ddr4-tester
  Experimental platform built around Xilinx Kintex-7 FPGA for development and customization of RAM controllers supporting RDIMM DDR4 RAM mo…
  ☆18Updated 3 months ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆81Updated last month
• aifoundry-org / et-platform
  ET Accelerator Firmware and Runtime
  ☆25Updated last week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆93Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated this week
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 11 months ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆63Updated 4 years ago
• riscvarchive / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• riscv-admin / graphics
  Graphics SIG organizational information
  ☆40Updated last year
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆122Updated this week
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆66Updated 8 months ago
• amaranth-lang / playground
  Playground for experimenting with and sharing short Amaranth programs on the web
  ☆20Updated 2 months ago
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆42Updated 3 months ago