Alternatives and similar repositories for subrisc

Users that are interested in subrisc are comparing it to the libraries listed below

• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆47Updated 4 years ago
• onikiri / onikiri2
  ☆39Updated last year
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆107Updated 3 years ago
• RuSys / Verugent
  Verilog generation tool written in Rust
  ☆59Updated 2 years ago
• moizumi99 / m99_riscv_emulator
  Simple RISC-V emulator
  ☆16Updated 5 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆36Updated 4 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• herumi / s_xbyak
  ASM generation tool for GAS/NASM/MASM with Xbyak-like syntax in Python
  ☆12Updated 7 months ago
• NextMicon / NextMiconIDE
  🛠️ Graphical IDE for NextMicon
  ☆28Updated last year
• ciniml / fpga_samples
  FPGA samples
  ☆23Updated last week
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 5 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 6 years ago
• sakura-internet / nvme-pcie-to-fabrics-proxy
  (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…
  ☆25Updated 2 years ago
• ainozaki / aarch64-emu
  Experimental AArch64 Emulator Written in C++
  ☆39Updated 2 years ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆54Updated 2 weeks ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• ocxtal / opa64
  Armv8 A64 Assembly & Intrinsics Guide Server
  ☆26Updated 2 years ago
• RIKEN-RCCS / MilvusVisor
  A thin-hypervisor that runs on aarch64 CPUs.
  ☆97Updated 3 weeks ago
• tamaroning / wanco
  WebAssembly AOT compiler with cross-CPU checkpoint/restore support
  ☆20Updated 3 months ago
• VLSI-JP / VLSI-JP.github.io
  ☆26Updated last week
• RIKEN-RCCS / riken_simulator
  This is the git repository for RIKEN simulator designed to simulate the binary code for Fujitsu A64FX.
  ☆36Updated 5 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆25Updated 11 months ago
• Alignof / hikami
  A lightweight Type-1 hypervisor for RISC-V H-extension, featuring RISC-V extension emulation.
  ☆52Updated last week
• msyksphinz-self / dydra
  ☆30Updated 2 years ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated last year
• msyksphinz-self / swimmer_rust
  RISC-V Simulator written in Rust
  ☆20Updated 5 years ago
• PG-MANA / Methylenix
  An operating system written in Rust
  ☆52Updated 2 months ago
• ep2k / epGB
  Game Boy / Game Boy Color emulator running on an FPGA
  ☆18Updated last year
• shioyadan / advanced-computer-organization
  ☆171Updated last year
• maekawatoshiki / long
  C++ Compiler
  ☆21Updated 3 years ago