sophgo / linux-riscvLinks
Linux kernel stable tree
☆34Updated this week
Alternatives and similar repositories for linux-riscv
Users that are interested in linux-riscv are comparing it to the libraries listed below
Sorting:
- ☆162Updated 3 weeks ago
- ☆33Updated this week
- Yet another Linux Distro for RISC-V!☆72Updated 2 months ago
- ☆96Updated 3 years ago
- ☆504Updated 2 months ago
- Buildroot customized for Xuantie™ RISC-V CPU☆46Updated 3 years ago
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆100Updated 3 months ago
- SOPHGO RISC-V Zero Stage BootLoader☆23Updated 3 weeks ago
- OpenXuantie - OpenC906 Core☆361Updated last year
- OpenEmbedded/Yocto layer for RISC-V Architecture☆400Updated this week
- ☆62Updated 4 years ago
- RISC-V Profiles and Platform Specification☆114Updated last year
- Linux kernel source tree☆43Updated 5 months ago
- Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-proce…☆200Updated last year
- RISC-V Architecture Profiles☆160Updated 5 months ago
- ☆70Updated 2 years ago
- sipeed wiki:https://wiki.sipeed.com☆133Updated this week
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆82Updated 3 years ago
- ☆38Updated 4 months ago
- Translate RISC-V Vector Assembly from v1.0 to v0.7☆34Updated 11 months ago
- Community's fork of Loongson PMON bootloader☆30Updated last year
- Documentation and status of UEFI on RISC-V☆60Updated 3 years ago
- Documentation of the RISC-V C API☆77Updated last week
- This repository provides a Linux kernel bootable on RISC-V boards from SiFive☆170Updated 5 years ago
- RISC-V Board and OS Support Matrix☆38Updated this week
- Firmware Of LoongArch Machines☆113Updated last week
- Risc-V journey thru containers and new projects☆281Updated last year
- A set of scripts to build a (somewhat) working Debian image for RISC-V.☆34Updated last year
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆66Updated 11 months ago