Alternatives and similar repositories for phaser

Users that are interested in phaser are comparing it to the libraries listed below

• cbalint13 / e-verest
  EVEREST: e-Versatile Research Stick for peoples
  ☆36Updated 2 years ago
• xobs / spibone
  Wishbone bridge over SPI
  ☆11Updated 6 years ago
• RobertBaruch / amaranth-tutorial
  ☆47Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• adamgreig / ecpdap
  ECPDAP allows you to program ECP5 FPGAs and attached SPI flash using CMSIS-DAP probes in JTAG mode.
  ☆70Updated 2 years ago
• kbob / nmigen-examples
  I want to learn [n]Migen.
  ☆44Updated 5 years ago
• icebreaker-fpga / icebreaker-litex-examples
  Example litex Risc-V SOC and some example code projects in multiple languages.
  ☆70Updated 2 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆88Updated last year
• lambdaconcept / lambdasoc
  ☆44Updated 9 months ago
• gregdavill / ecpprog
  Programmer for the Lattice ECP5 series, making use of FTDI based adaptors
  ☆90Updated last year
• QuickLogic-Corp / quicklogic-fpga-toolchain
  Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP
  ☆40Updated 4 years ago
• tomverbeure / pdm
  ☆21Updated 4 years ago
• RobertBaruch / amaranth-exercises
  ☆25Updated last year
• tvelliott / dsp_ice
  ICE40 8K FPGA / STM32F4 development system
  ☆62Updated 8 years ago
• QuickLogic-Corp / EOS-S3
  Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC
  ☆27Updated 4 years ago
• adamgreig / ffp
  iCE40 FPGA, SPI flash, and CMSIS-DAP SWD programmer
  ☆70Updated 4 years ago
• korken89 / ovio_core
  ☆29Updated 4 years ago
• devbisme / myhdlpeek
  Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
  ☆40Updated last year
• adamgreig / daqnet
  ☆63Updated 5 years ago
• olofk / observer
  ☆42Updated 5 years ago
• azonenberg / protohdl
  Streaming FPGA/ASIC code generator for Google Protocol Buffers.
  ☆17Updated 4 years ago
• ArrowElectronics / AnalogMAX
  This repository is dedicated to the Arrow AnalogMax family of products. Please review the Wiki content to access technical information …
  ☆12Updated 4 years ago
• lambdaconcept / amaranth-to-litex
  Use amaranth-to-litex to simply import Amaranth code into a Litex project.
  ☆15Updated last year
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆18Updated 4 years ago
• psychogenic / microcotb
  micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
  ☆17Updated 9 months ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆85Updated last year
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 2 weeks ago