Alternatives and similar repositories for pyPCIe

Users that are interested in pyPCIe are comparing it to the libraries listed below

• CESNET / ndk-fpga
  Network Development Kit (NDK) for FPGA cards with example application
  ☆63Updated last week
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆69Updated 8 months ago
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆28Updated 5 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• slaclab / axi-pcie-core
  ☆23Updated this week
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆26Updated 5 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆65Updated 2 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• open-power / snap
  CAPI SNAP Framework Hardware and Software
  ☆110Updated 4 years ago
• quic / qbox
  Qbox
  ☆58Updated 2 weeks ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 3 months ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆106Updated 7 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆26Updated 3 years ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆36Updated 3 weeks ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆111Updated 3 months ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆154Updated 3 months ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆71Updated last year
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆39Updated 7 years ago
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆55Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆29Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆86Updated 11 months ago
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• ucsdsysnet / Rosebud
  Framework for FPGA-accelerated Middlebox Development
  ☆45Updated 2 years ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆129Updated 4 years ago