Alternatives and similar repositories for rvemu-for-book

Users that are interested in rvemu-for-book are comparing it to the libraries listed below

• d0iasm / rvemu
  RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
  ☆850Updated 11 months ago
• takahirox / riscv-rust
  RISC-V processor emulator written in Rust+WASM
  ☆657Updated 2 years ago
• moratorium08 / osmium
  A toy operating system written in Rust on RISC V(rv32im)
  ☆204Updated 2 years ago
• d0iasm / book.rvemu
  The book "Writing a RISC-V Emulator from Scratch in 10 Steps".
  ☆130Updated 2 years ago
• sgmarz / osblog
  The Adventures of OS
  ☆546Updated 2 years ago
• siriusdemon / Rare
  Build your own Riscv Emulator in Rust.
  ☆105Updated 2 years ago
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆706Updated 3 years ago
• mit-pdos / RVirt
  RISC-V hypervisor written in Rust
  ☆357Updated 5 years ago
• riscv-non-isa / riscv-sbi-doc
  Documentation for the RISC-V Supervisor Binary Interface
  ☆403Updated last week
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆142Updated last year
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆760Updated last week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆632Updated 2 weeks ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆428Updated 11 months ago
• diodesign / diosix
  A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
  ☆196Updated 4 months ago
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆488Updated 6 months ago
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆266Updated 9 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆267Updated this week
• riscv-software-src / opensbi
  RISC-V Open Source Supervisor Binary Interface
  ☆1,197Updated this week
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆97Updated 6 months ago
• skyzh / core-os-riscv
  🖥️ An xv6-like operating system on RISC-V with multi-core support. Documentation available online.
  ☆313Updated 3 years ago
• rcore-os / virtio-drivers
  VirtIO guest drivers in Rust.
  ☆254Updated this week
• riscv-software-src / riscv-tests
  ☆998Updated 2 weeks ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆88Updated 4 years ago
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆64Updated last year
• andrewhalle / byo-linker
  Build your own - linker
  ☆198Updated 4 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆149Updated last week
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆186Updated last week
• mnurzia / rv
  32-bit RISC-V CPU in ~800 lines of C89
  ☆615Updated last year
• riscv / sail-riscv
  Sail RISC-V model
  ☆538Updated this week
• maekawatoshiki / sericum
  (Toy) Compiler Infrastructure influenced by LLVM written in Rust
  ☆400Updated 4 years ago