该项目主要展示了一般的claude code配置方法，并结合官方插件，将claude code嵌入vscode中，此外，实现了claude code与matlab之间的通信，并集成在vscode中，从而达到自动matlab代码编辑，脚本生成，结果保存，代码自动debug等功能
☆27May 22, 2026Updated 5 months ago
Alternatives and similar repositories for Claude-code-Vscode-matlab-
Users that are interested in Claude-code-Vscode-matlab- are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 学习过程的一些简单记录 数字IC、C++、FPGA☆11Mar 7, 2025Updated last year
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated last year
- A RISC-V processor☆14Dec 11, 2018Updated 7 years ago
- Speech corpora for the speech recognition evaluation system☆21Mar 20, 2018Updated 8 years ago
- Run MATLAB® using AI applications with the official MATLAB MCP Server from MathWorks®. This MCP server for MATLAB supports a wide range o…☆1,782Oct 30, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Mar 22, 2024Updated 2 years ago
- Source code for "Intelligent Reflecting Surface Operation under Predictable Receiver Mobility: A Continuous Time Propagation Model" by B…☆39Sep 23, 2020Updated 6 years ago
- 复微杯☆18Aug 7, 2024Updated 2 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 6 months ago
- Deploy llama2.c on the OpenLA500 SoC with custom AI accelerator (FPGA)☆24Jun 16, 2026Updated 4 months ago
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1 in TSMC 16nm☆23Sep 27, 2026Updated last month
- SystemVerilog for Verification A Guide to Learning the Testbench Language Features Third Edition中文翻译☆23Jan 10, 2022Updated 4 years ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆34Aug 9, 2024Updated 2 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆29Jun 30, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆32Mar 4, 2023Updated 3 years ago
- Simulation code for “Reconfigurable Intelligent Surfaces: A Signal Processing Perspective With Wireless Applications” by Emil Björnson, H…☆65Jan 10, 2022Updated 4 years ago
- Type II Reflexxes Motion Library☆57Apr 20, 2015Updated 11 years ago
- CodexHub is a multi-server management console for Codex App SSH workflows. CodexHub 是面向 Codex App SSH 工作流的多服务器群管理控制台。☆45Oct 19, 2026Updated 2 weeks ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆41Aug 13, 2024Updated 2 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆35May 29, 2024Updated 2 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆42Nov 30, 2022Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆58May 10, 2021Updated 5 years ago
- ☆55Aug 10, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆62Feb 18, 2019Updated 7 years ago
- Saturation in the Null Space (SNS) Inverse Kinematic Library☆113Mar 4, 2020Updated 6 years ago
- ☆51May 11, 2022Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆62Sep 14, 2016Updated 10 years ago
- Admittance control law to generate desired motion of an end-effector (twist), given a desired or external wrench for a velocity-controlle…☆111Aug 26, 2020Updated 6 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Jun 1, 2022Updated 4 years ago
- 龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）☆66Mar 6, 2024Updated 2 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆77Aug 10, 2024Updated 2 years ago
- ☆156Oct 13, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆84Jan 19, 2016Updated 10 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆124Updated this week
- AXI总线连接器☆111Mar 26, 2020Updated 6 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆139Dec 17, 2023Updated 2 years ago
- CPU Design Based on RISCV ISA☆148Jun 14, 2024Updated 2 years ago
- Motion Planning around Obstacles with Convex Optimization by Marcucci et al, 2023☆276Jul 9, 2024Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆150May 14, 2021Updated 5 years ago