blue7wings / clash-tunView external linksLinks
在Linux环境中设置clash tun模式,以便达到全局代理的功能
☆18May 21, 2022Updated 3 years ago
Alternatives and similar repositories for clash-tun
Users that are interested in clash-tun are comparing it to the libraries listed below
Sorting:
- 《计算机设计与实践》测试框架☆17Jun 28, 2022Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 3 months ago
- ☆12Aug 12, 2022Updated 3 years ago
- [READ ONLY] Subtree split of the siyuan-packages-monorepo (see https://github.com/Zuoqiu-Yingyi/siyuan-packages-monorepo)☆12Jan 23, 2024Updated 2 years ago
- 经典的嵌入式OS - ucos-II 2.52版本全注释,仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- WebSocket在线测 试工具☆10Apr 23, 2025Updated 9 months ago
- gem5 FS模式实验手册☆44Mar 8, 2023Updated 2 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- ☆13May 8, 2025Updated 9 months ago
- 函数的分段线性拟合☆10Nov 15, 2017Updated 8 years ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 4 months ago
- This is the course taught by Prof.John Shen and Prof. Onur Mutlu from CMU☆11May 13, 2016Updated 9 years ago
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Jan 26, 2020Updated 6 years ago
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- 开源 webhook 代理服务,基于 Hono 框架和 Cloudflare Workers 构建。将 webhook 事件实时转换为 WebSocket 或 SSE 事件流。☆17Nov 15, 2025Updated 2 months ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- An unnecessarily tiny and minimal implementation of GPT-2 in NumPy.☆11Feb 12, 2023Updated 3 years ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- onebot v11 adapter in plugin☆10Mar 5, 2023Updated 2 years ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- simple 4-BIT CPU with 74-serials chip,origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- livecoding talk for oscon 2018☆10Jul 18, 2018Updated 7 years ago
- ☆10Nov 12, 2019Updated 6 years ago
- 定时执行☆11Oct 7, 2024Updated last year
- ☆12Feb 6, 2026Updated last week
- Simple PyTorch profiler that combines DeepSpeed Flops Profiler and TorchInfo☆11Feb 12, 2023Updated 3 years ago
- ☆15Dec 17, 2025Updated last month
- Website template for meme collection.☆10May 28, 2025Updated 8 months ago
- BTB-X HPCA23 code☆13Jan 6, 2023Updated 3 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated last year
- An IPKVM board for OrangePi Zero.☆12Dec 1, 2022Updated 3 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year