UoS-EEC / fusedLinks
Fused: Full-System Simulation of Energy-Driven Computers
☆16Updated 3 years ago
Alternatives and similar repositories for fused
Users that are interested in fused are comparing it to the libraries listed below
Sorting:
- RISC-V Virtual Prototype☆45Updated 4 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆158Updated 6 months ago
- RISC-V Virtual Prototype☆182Updated last year
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆124Updated this week
- Tools for analyzing and browsing Tarmac instruction traces.☆79Updated last month
- Brief SystemC getting started tutorial☆95Updated 6 years ago
- Constrained random stimuli generation for C++ and SystemC☆52Updated 2 years ago
- ☆88Updated 2 years ago
- gdb python scripts for SystemC design introspection and tracing☆32Updated 6 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated 2 weeks ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- A header only C++11 library for functional coverage☆36Updated 3 years ago
- A set of benchmarks chosen to show the energy consumption of embedded devices under different conditions☆70Updated 2 years ago
- A modeling library with virtual components for SystemC and TLM simulators☆176Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 9 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 3 weeks ago
- Example code for Modern SystemC using Modern C++☆68Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- ☆67Updated 2 years ago
- PCI Express controller model☆71Updated 3 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- New release of the systemc libraries☆123Updated 13 years ago
- ☆13Updated 3 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 9 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- hardware library for hwt (= ipcore repo)☆43Updated last month