Fused: Full-System Simulation of Energy-Driven Computers
☆17Apr 14, 2022Updated 3 years ago
Alternatives and similar repositories for fused
Users that are interested in fused are comparing it to the libraries listed below
Sorting:
- My amp pcbs☆11Jul 28, 2024Updated last year
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- ☆12May 21, 2024Updated last year
- FreeRTOS Multicore for the Cortex-M3(Ducati) on Pandaboard☆23May 13, 2013Updated 12 years ago
- ☆11Oct 10, 2018Updated 7 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- ☆11Apr 3, 2017Updated 8 years ago
- A macrospin simulation tool for nanoparticles☆12Dec 4, 2024Updated last year
- ☆13Oct 9, 2013Updated 12 years ago
- basic command line utility to automate the Saleae Logic software using the ppannuto python-saleae library☆41Mar 11, 2022Updated 3 years ago
- Sargon Chess for CP/M☆11May 12, 2021Updated 4 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- JSON Schema validation library for Robot Framework☆10Jul 2, 2019Updated 6 years ago
- A tool for modeling FSMs by VHDL or Verilog☆11Updated this week
- Main repo of the OOP class☆11Oct 16, 2017Updated 8 years ago
- Windows 2000 Source Code☆11Aug 3, 2024Updated last year
- Xilinx Platform cable USB and impact on linux without windrvr by Michael Gernoth☆11Apr 17, 2014Updated 11 years ago
- FreeRTOS with Earlier Deadline First( EDF ) task scheduling.☆12Jul 13, 2017Updated 8 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 13 years ago
- Xilinx CPLD replacement for the Commodore Amiga Amber custom chip☆14Oct 31, 2025Updated 4 months ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- ☆11Oct 5, 2015Updated 10 years ago
- Utilities for testing Kubernetes installations☆12Jan 16, 2018Updated 8 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- Set of Git hooks for pep8, pyflakes and trac integration.☆20Jul 25, 2020Updated 5 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- Audio libs for load and play some audio files☆10Jan 3, 2021Updated 5 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- A vhdl package for reading and writing bitmap files.☆11Jan 9, 2018Updated 8 years ago
- PlayStation GPU (WIP)☆17Oct 3, 2023Updated 2 years ago
- Firmware for Xilinx Platform Cable 1 USB Jtag adapter☆10Jul 24, 2016Updated 9 years ago
- Reproducible hardened Linux images for confidential computing and safe MEV☆17Updated this week
- Network protocol libraries for VHDL test benches☆13Jan 11, 2026Updated last month
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Mirror of NetBSD sources useful with rump kernels☆13Mar 23, 2017Updated 8 years ago
- VHDL source file project for a hardware in the loop simulation of a permanen magnet motor with field oriented control design☆11Nov 22, 2022Updated 3 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last month
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆10Jun 1, 2021Updated 4 years ago