ThinkOpenly / sailLinks
Sail architecture definition language
☆12Updated 5 months ago
Alternatives and similar repositories for sail
Users that are interested in sail are comparing it to the libraries listed below
Sorting:
- ☆13Updated 2 months ago
- RISC-V SST CPU Component☆24Updated 2 weeks ago
- The gem5 Bootcamp 2022 environment. Archived.☆36Updated last year
- RISC-V Virtual Prototype☆44Updated 3 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆38Updated last month
- ordspecsim: The Swarm architecture simulator☆25Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated 2 months ago
- ☆92Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- upstream: https://github.com/RALC88/gem5☆32Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆36Updated last month
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆21Updated last year
- Xtext project to parse CoreDSL files☆20Updated 5 months ago
- The official repository for the gem5 resources sources.☆72Updated 2 months ago
- ☆44Updated 6 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- ☆59Updated last week
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last month
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆24Updated 7 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- ☆20Updated last month
- ☆25Updated last year
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆23Updated last year
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆32Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 9 months ago
- Microarchitecture diagrams of several CPUs☆37Updated 2 weeks ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 6 months ago