A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.
☆100Jan 10, 2024Updated 2 years ago
Alternatives and similar repositories for FmcPGA
Users that are interested in FmcPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The automation major at SUSTech. Courses, competitions, further studies, and employment related to the automation major. 南科大自动化专业非官方主页☆21Aug 12, 2025Updated 11 months ago
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆35Jun 16, 2023Updated 3 years ago
- Typst template for theses in Southern University of Science and Technology (SUSTech).☆34Jul 2, 2026Updated 3 weeks ago
- Experiment reports for the course Signals and Systems.☆17Sep 4, 2022Updated 3 years ago
- 不用校园卡开南科大宿舍门hack sustech dormitory door☆28Sep 14, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 把b站字幕一次性全部显示或下载☆43Jul 25, 2025Updated last year
- ☆89Sep 2, 2025Updated 10 months ago
- Template for assignment 2 of SUSTech CS209, 23 spring semester.☆10Apr 18, 2023Updated 3 years ago
- Digital Signal Processing LABs for SUSTECH 2020 FALL (EE323).☆15Jan 2, 2021Updated 5 years ago
- Course materials of CS329 Machine Learning(H), SUSTech☆23Jan 15, 2024Updated 2 years ago
- 《人工智能法规、伦理与社会影响》书稿☆14Aug 28, 2021Updated 4 years ago
- 南方科技大学本科生毕业论文 LaTeX 模板☆345Mar 8, 2026Updated 4 months ago
- A QQ bot with lots of functions☆32Jun 16, 2026Updated last month
- Genetic Algorithm based hyperparameter tuning tools for Reversi gaming AI (MIninax search with alpha-beta pruning)☆12Jan 25, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆36Jun 1, 2026Updated last month
- CS302 OS Notes☆10Jun 17, 2021Updated 5 years ago
- ☆44Dec 20, 2024Updated last year
- 计系小群 群信息与群文件☆25Mar 28, 2023Updated 3 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- ☆15Jun 27, 2024Updated 2 years ago
- CS109-23S course project example☆16May 30, 2023Updated 3 years ago
- Generate Linux Perf event tables for Apple Silicon☆18Dec 16, 2025Updated 7 months ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Jul 4, 2026Updated 3 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- VHDL implementation of CCSDS123 compression standard☆10Mar 30, 2019Updated 7 years ago
- All the important parts of SUSTech Computer Science Courses☆347Feb 20, 2025Updated last year
- Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation c…☆16Sep 7, 2021Updated 4 years ago
- Implement matrix multiplication using SIMD.☆13Nov 19, 2016Updated 9 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Nov 19, 2023Updated 2 years ago
- [TMI'22] "AADG: Automatic Augmentation for Domain Generalization on Retinal Image Segmentation".☆70Dec 20, 2023Updated 2 years ago
- Mirror of http://svn.linuxvirtualserver.org/repos/ipvsadm☆13Dec 30, 2015Updated 10 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Open-source RTL IP developement for IIR/FIR filters in SystemVerilog, along with the C model and verification IP in UVM☆15Jul 8, 2026Updated 2 weeks ago
- ☆17Jul 23, 2025Updated last year
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆15Mar 13, 2022Updated 4 years ago
- Vivado诸多IP，包括图像处理等☆233Jul 28, 2024Updated last year
- Eclipse based IDE for RISC-V bare metal software development.☆20Nov 21, 2019Updated 6 years ago
- ☆43Jan 14, 2022Updated 4 years ago
- For Course CS205 'C/C++ Program Design' at Southern University of Scicence and Technology, China☆70Dec 31, 2021Updated 4 years ago