Gralerfics / FmcPGA
A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.
☆74Updated last year
Alternatives and similar repositories for FmcPGA:
Users that are interested in FmcPGA are comparing it to the libraries listed below
- A smart watch based on STM32F405RGT6.☆14Updated last year
- An exquisite superscalar RV32GC processor.☆149Updated last month
- Project for SUSTech Java course. A raytracing OthellooO game based on LWJGL.☆9Updated 9 months ago
- ☆133Updated 5 months ago
- RISC-V Development Boards Wandering Project. It is part of the Jiachen Project.☆34Updated this week
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆57Updated 2 years ago
- ☆79Updated last week
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 11 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆46Updated 3 months ago
- ☆22Updated 2 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated this week
- 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设,支持运行主线Linux。A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals ar…☆82Updated 4 months ago
- ☆53Updated last month
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆113Updated 2 years ago
- ☆63Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆28Updated 10 months ago
- ☆31Updated last year
- ☆68Updated last month
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Updated 10 months ago
- a framework for building hardware verification platform using software method☆14Updated last week
- ☆23Updated 3 weeks ago
- NJU Virtual Board☆255Updated last month
- Official website for Jiachen Project (甲辰计划).☆54Updated 2 months ago
- ☆61Updated 6 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆111Updated 3 months ago
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆30Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆168Updated 3 years ago
- 一生一芯的信息发布和内容网站☆128Updated last year
- A riscv emulator.☆18Updated last year
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆77Updated 7 months ago