Alternatives and similar repositories for digial-ising

Users that are interested in digial-ising are comparing it to the libraries listed below

• olofk / corescore
  CoreScore
  ☆166Updated last week
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆142Updated 6 months ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆72Updated 2 weeks ago
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆185Updated last month
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆48Updated last week
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆231Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆86Updated 10 months ago
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆143Updated last year
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆62Updated last month
• stnolting / neoTRNG
  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
  ☆203Updated last month
• mosscomp / moss
  A computer for human beings.
  ☆47Updated 11 months ago
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆165Updated last year
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆116Updated this week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆153Updated last week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆301Updated this week
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆120Updated this week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• mineda-support / ICPS2023_5
  ☆57Updated 3 months ago
• TinyTapeout / tt06-verilog-template
  Submission template for Tiny Tapeout 6 - Verilog HDL Projects
  ☆34Updated last year
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆90Updated last month
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• chipsalliance / silicon-notebooks
  ☆173Updated 2 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆201Updated last week
• adonairc / tt07-dda-van-der-pol
  DDA solver for the van der Pol oscillator using 16-bit posits
  ☆28Updated 9 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆107Updated last month
• ArcSpecter / rapidvpi
  Blazingly fast, modern C++ API using coroutines for efficient RTL verification and co-simulation via the VPI interface
  ☆17Updated 3 weeks ago