Alternatives and similar repositories for digial-ising

Users that are interested in digial-ising are comparing it to the libraries listed below

• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆138Updated 3 months ago
• olofk / corescore
  CoreScore
  ☆158Updated 5 months ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆68Updated this week
• chipsalliance / silicon-notebooks
  ☆170Updated last year
• stnolting / neoTRNG
  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
  ☆193Updated 3 weeks ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆86Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 9 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆83Updated 7 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆188Updated last month
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆48Updated last month
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆37Updated 3 weeks ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆94Updated 2 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆114Updated this week
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆144Updated 9 months ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆147Updated last week
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆49Updated this week
• msoeken / cirkit
  A circuit toolkit
  ☆103Updated 5 years ago
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆173Updated last month
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆220Updated last year
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆112Updated 2 weeks ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆84Updated last month
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆238Updated last month
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆56Updated 2 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆62Updated 5 months ago
• mosscomp / moss
  A computer for human beings.
  ☆44Updated 8 months ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆47Updated 2 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆79Updated 3 years ago
• mineda-support / ICPS2023_5
  ☆53Updated last week