利用XIRR算法计算基金定投年化收益率
☆12Jul 6, 2023Updated 2 years ago
Alternatives and similar repositories for FundXirr
Users that are interested in FundXirr are comparing it to the libraries listed below
Sorting:
- 微信相关定时爬虫任务。☆11Jul 12, 2018Updated 7 years ago
- A simple Vue image cropping component.☆15Apr 17, 2019Updated 6 years ago
- ☆11May 31, 2016Updated 9 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- Official repository for the WACV 2024 paper "Multi-view Classification with Hybrid Fusion and Mutual Distillation"☆15Jan 16, 2024Updated 2 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- 200W 铝基板 加热台控制器，具备PID控制，PWM输出，卡尔曼滤波☆11Oct 30, 2022Updated 3 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- 一个开源的基于stm32的磁悬浮项目☆15Nov 21, 2023Updated 2 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Automatically Detect Out of focus and blurry images☆10Nov 18, 2016Updated 9 years ago
- ☆10Jun 28, 2016Updated 9 years ago
- ☆11Nov 12, 2024Updated last year
- Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- 使用verilog编写sdram控制器☆12Jun 22, 2019Updated 6 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- PyQt Windows notifier show at bottom right of the desktop screen☆10May 18, 2022Updated 3 years ago
- ☆10Aug 15, 2019Updated 6 years ago
- Large-screen visualization template（大屏可视化模板）☆12Apr 22, 2021Updated 4 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- 自用青龙库☆14Jul 16, 2025Updated 7 months ago
- Create your custom Qt + PyQt SDK for multiple platforms☆10Jun 7, 2019Updated 6 years ago
- 电子设计竞赛☆15Dec 4, 2021Updated 4 years ago
- (翻译)JavaScript轻量级函数式编程☆14Sep 30, 2019Updated 6 years ago
- A Python app that converts vocal recordings into MIDI files. Transform your singing into digital music!☆17Nov 1, 2025Updated 4 months ago
- Jax implementation of a flexible audio loudness meter in Python with implementation of ITU-R BS.1770-4 loudness algorithm☆12Jan 29, 2025Updated last year
- In this video, we gonna learn how to create interactive web design using simple html and css☆10Aug 5, 2019Updated 6 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- GPS&BD2卫星导航系统模拟信号源☆11Aug 6, 2015Updated 10 years ago
- This is a script for converting all Excel based formats to prettified XML format☆10Dec 13, 2017Updated 8 years ago
- 实现用户在不同设备、不同地点多人同步听歌，使用Websocket协议实现音乐的时间、播放暂停、切歌数据同步。技术栈：Vue.js ,Websocket, Spring boot☆10Jul 2, 2021Updated 4 years ago
- Wireless Industrial Condition Monitoring solution☆14Jan 17, 2025Updated last year
- ☆14Jun 30, 2019Updated 6 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库！☆16May 9, 2024Updated last year
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- ☆10May 26, 2023Updated 2 years ago