Verilog Package for Sublime Text 2/3
☆23Jan 27, 2024Updated 2 years ago
Alternatives and similar repositories for sublime-verilog
Users that are interested in sublime-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 使用DDS芯片AD9914产生线性扫频信号☆13Dec 9, 2020Updated 5 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 13 years ago
- An inserted spectrum analyzer based on Zynq-7000, which uses scheme for FPGA+ARM standalone.☆27Apr 30, 2023Updated 3 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 11 years ago
- FPGA based signal generator☆14Dec 25, 2023Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- python_learning☆16May 18, 2022Updated 4 years ago
- ☆24Jan 25, 2021Updated 5 years ago
- Use FPGA to Transfer Image with Gigabits Ethernet☆19Dec 2, 2020Updated 5 years ago
- Must-have verilog systemverilog modules☆39May 1, 2022Updated 4 years ago
- ☆13Jan 5, 2014Updated 12 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆16Nov 4, 2020Updated 5 years ago
- BPI-EAI80 AIoT board use Edgeless EAI80 chip design☆16Dec 26, 2022Updated 3 years ago
- ☆12Jun 6, 2019Updated 7 years ago
- C++ Drivers for STM☆10Mar 3, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- 1G eth UDP / IP Stack☆10Jul 17, 2014Updated 12 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- ☆15Apr 18, 2023Updated 3 years ago
- Simulation of a Brushless DC Motor☆12Jan 7, 2017Updated 9 years ago
- A usb FPGA board based Logic analyzer (逻辑分析仪)☆18Nov 14, 2022Updated 3 years ago
- Demo for Melexis MLX90640 sensor using mikromedia 7 for STM32F7☆19Dec 9, 2021Updated 4 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- A first-in-first-out for bytes, like kfifo in Linux.☆19Apr 15, 2017Updated 9 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- 天猫秒杀插件☆11Nov 10, 2017Updated 8 years ago
- RS-485 / CDBUS JPEG Camera☆19Aug 6, 2026Updated last month
- Software USB-LS 2 hosts on stm32f030 gpio☆13Mar 17, 2021Updated 5 years ago
- RFNoC out-of-tree module for a channelizer☆17Mar 14, 2018Updated 8 years ago
- Modification to legalise the Xiaomi Mi Scooters in The Netherlands☆14Apr 12, 2023Updated 3 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆17Jun 24, 2026Updated 2 months ago
- Arduino Based Simple Closed Loop Motor Control library☆14Oct 7, 2020Updated 5 years ago
- STM32 Driver MLX90640 IR Sensor☆16Dec 22, 2018Updated 7 years ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CDBLOG source code and articles backup for my blog, articles also could be read at here directly.☆19Sep 9, 2026Updated last week
- This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human er…☆18Mar 12, 2026Updated 6 months ago
- Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and S…☆15Mar 26, 2014Updated 12 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 6 years ago
- A four-channel narrowband SDR receiver based around the Mirics MSi001, MAX11131 and FX2LP.☆16Jan 1, 2021Updated 5 years ago
- verilog modules☆16May 4, 2020Updated 6 years ago
- A low-power, low-cost, highly-portable software defined radio platform.☆20Feb 19, 2018Updated 8 years ago